Electronic timepiece

ABSTRACT

An electronic timepiece includes a frequency supply for providing a relatively high frequency time base signal, a frequency converter responsive to the time base signal to provide a relatively low frequency time unit signal, and timekeeping means responsive to the time unit signal to provide current time information. The current time information is corrected and displayed. A calculation command signal is generated and enables a circuit means to produce, in response to the time unit signal, a frequency error signal indicative of an error in the frequency of the time unit signal. A gain/loss adjustment signal is generated in response to the frequency error signal, and a frequency adjusting circuit is provided for adjusting the frequency of the time unit signal in response to the gain/loss adjustment signal.

This is a Divisional of application Ser. No. 626,791 filed Oct. 29,1975, now U.S. Pat. No. 4,150,535 issued Apr. 24, 1979.

This invention relates in general to timepiece systems and, moreparticularly, to a solid state electronic timepiece.

In recent years, considerable efforts have been directed toward thedevelopment of solid state electronic timepieces which utilize no movingparts for performing the timing function. In many instances, these haveutilized a crystal controlled oscillator as a frequency standard and adisplay device for displaying the current time in digital mode. In viewof this display mode, various attempts have heretofore been made to havethe electronic timepiece provided with multiple functions, such asindication of date or alarm time data. Since, however, the additionalinformation is usually displayed on the same display surface on whichthe hours, minutes and seconds are displayed, it is inconvenient for thewearer of the watch to identify the necessary information. Further, inorder that the electronic timepiece provide multiple functions, it mustbe provided with additional components and associated parts, which cancause mulfunctions and increased size.

Another problem encountered is that the power consumption is necessarilyincreased because of the need to additional components.

It is, therefore, an object of the present invention to provide a novelsolid state electronic timepiece which provides multiple functions inaddition to indication of hours, minutes and seconds.

It is another object of the present invention to provide a solid stateelectronic timepiece in which stored data may be displayed such that thesame display elements may be used for indicating hours, minutes andseconds and various other information.

It is another object of the present invention to provide a solid stateelectronic timepiece to which an option system may be connected, to giveadditional functions such as a multi-alarm capability, an automaticgain/loss adjusting facility, an electronic calculator facility, etc.,in addition to the normal timekeeping function.

It is a further object of the present invention to provide a solid stateelectronic timepiece which is sufficiently small in size to be ofpractical use, yet provide accurate time indication as well as ease ofoperation.

These and other objects, features and advantages of the presentinvention will become more apparent from the following description whentaken the accompanying drawings, in which:

FIG. 1 is a schematic block diagram of a solid state electronictimepiece according to the present invention;

FIG. 2 is a view illustrating the general constitution of the electronictimepiece shown in FIG. 1;

FIG. 3 is a simplified block diagram of electric circuitry for thetimepiece shown in FIG. 2;

FIGS. 4A, 4B and 4C are detail block diagrams of electric circuitry forthe timepiece shown in FIG. 3;

FIG. 5 is a preferred example of the time standard oscillator shown inFIGS. 4A, 4B and 4C;

FIG. 6 is an example of waveforms obtained by the circuit shown in FIG.5;

FIGS. 7A and 7B show a preferred example of the frequency synthesizershown in FIGS. 4A, 4B and 4C;

FIG. 8 is a view showing the relationship between clock pulses andtiming pulses obtained by the frequency synthesizer shown in FIGS. 7Aand 7B;

FIGS. 9 and 10 illustrate waveforms generated by the frequencysynthesizer of FIGS. 7A and 7B;

FIGS. 11A and 11B show details of circuitry for the timekeeping registerof FIGS. 4A, 4B and 4C;

FIG. 12 shows details of electric circuitry for the control unit shownin FIGS. 4A, 4B and 4C;

FIG. 13 is an example of the flexible circuit shown in FIGS. 4A, 4B and4C;

FIG. 14 is a schematic diagram of a shift register shown in FIGS. 11 and12;

FIG. 15 shows an example of the logic level setting circuit shown inFIG. 12;

FIG. 16 shows details of a circuit arrangement for the timer used in thecontrol unit of FIG. 12;

FIG. 17 is a schematic view of an example of a wristwatch embodying thepresent invention;

FIG. 18 is a cross section illustrating the relationship between theposition of the crown and associated parts;

FIG. 19 is a view showing the operating mode of the crown and switchesshown in FIG. 18;

FIGS. 20A and 20B show detials of an example of circuitry for the datamodulating unit shown in FIGS. 4A, 4B and 4C;

FIG. 21 shows a preferred example of the alarm unit shown in FIGS. 4A,4B and 4C;

FIGS. 22A, 22B and 22C are detail block diagrams of the display driverand associated parts;

FIG. 23 is a schematic view illustrating an example of the display face;

FIG. 24A shows details of electric circuitry for the level shifter shownin FIGS. 22A, 22B and 22C;

FIG. 24B is similar to FIG. 24A but shows a different example of thelevel shifter;

FIG. 24C is an example of the decoder shown in FIGS. 22A, 22B and 22C;

FIG. 25 shows the general concept of an option system according to thepresent invention;

FIG. 26 is a simplified block diagram illustrating a preferredembodiment of the option system according to the present invention;

FIGS. 27A, 27B and 27C show detail block diagrams for an example of theoption system shown in FIG. 26;

FIGS. 28A and 28B are circuit diagrams of the shift register ringcircuit of FIG. 26;

FIG. 29 is an example of a clock pulse control gate shown in FIGS. 27A,27B and 27C;

FIG. 30 is a preferred example of a data demodulating circuit shownFIGS. 27A, 27B and 27C;

FIG. 31 is an example of a composite pulse regenerating circuit;

FIG. 32 is an example of a timing pulse regenerating circuit shown inFIGS. 27A, 27B and 27C;

FIG. 33 shows a current time display state detecting circuit;

FIG. 34 shows a synchronizing signal regenerating circuit;

FIG. 35 shows an alarm time display state detecting circuit;

FIG. 36 shows an example of a composite pulse generator;

FIG. 37 shows a combined signal generator;

FIG. 38 shows a manual shift control circuit;

FIG. 39 shows a symbol setting circuit;

FIG. 40 shows an example of an input control circuit;

FIG. 41 shows an output control circuit;

FIG. 42 shows an example of an alarm time and current time coincidencedetecting circuit;

FIG. 43 shows an example of a date alarm and date coincidence detectingcircuit;

FIG. 44 shows an example of a shift register stop control circuit;

FIG. 45 shows a "flexible" circuit;

FIG. 46 shows an example of a date gate control circuit;

FIG. 47 shows an example of an input analyzing circuit;

FIG. 48 shows an example of a calculating circuit;

FIG. 49 shows an example of a gain/loss adjusting pulse generator;

FIG. 50 shows waveforms of a bistable circuit used in the option systemaccording to the present invention;

FIG. 51 shows an operating mode of the shift register shown in FIGS. 28Aand 28B;

FIG. 52 shows waveforms utilized for the manual shift control circuitshown in FIG. 38;

FIG. 53 shows waveforms of the outputs generated by the synchronizingsignal regenerating circuit;

FIG. 54 shows a modification of the date gate counter shown in FIG. 46;

FIG. 55 shows the relationship between various timing signals;

FIG. 56 is a schematic diagram illustrating modes of transferring data;and

FIG. 57 shows the relationship between various pulses used in the optionsystem according to the present invention.

FIG. 1 shows a basic block diagram for a timepiece system in accordancewith the present invention. It consists of a standard timekeeping system10 and, an option system 12, which may or may not be included. Thestandard timekeeping system 10 provides various functions such astimekeeping and display of data, and is designed to be readilyinterconnected with the option system, enabling it to perform additionalfunctions.

As shown in FIG. 2, the standard timekeeping system 10 comprises afrequency standard crystal oscillator, which provides an accurate stablefrequency. This is applied to a frequency synthesizer 16, which dividesthe oscillator output down to give a time unit signal. The frequencysynthesizer also produces various timing signals, which serve to controlthe operation of the basic timekeeping system. The time unit signal isinput to a timekeeping register 18, where it is added into the registercontents, to perform the timekeeping function. Time data stored in thisregister is transferred via a display driver 20 to the display 22. Thisdisplay can be of liquid crystal type, etc. The various components ofthe standard timekeeping system are supplied from an electrical powersource, such as a silver oxide battery. If an option system 12 isinterconnected with the standard timekeeping system 10, the power sourcemay also supply the components of the option system. The standardtimekeeping system also includes a control system 26, whose function isto control the timekeeping register, and which may further control theoperation of the frequency converter and display driver 20 in variousways which will be described subsequently in detail.

The option system 12 is designed to storedata, for example, variousdifferent times and dates for the initiation of alarm signal to the userof the timepiece. This alarm data can be written into the option systemvia the timekeeping register of the standard timekeeping system, so thatwhen the alarm time option system is utilized, it is not necessary toconnect additional external control devices. Option system 12 alsoserves to generate various control signals, as will be described indetail subsequently, and can be set to produce a gain/loss adjustingsignal. The gain/loss adjusting signal is applied to an input of thestandard timing oscillator, as shown by the broken line in FIG. 2. Inthe illustrated embodiment, however, the gain/loss adjusting signal isapplied to the frequency synthesizer 16. In addition, various types ofdata stored in option system 12 are supplied via the timekeepingregister to the display driver and hence the display. Since this data isstored in a separate storage register (in the option unit), it has noeffect upon the normal timekeeping function. Although in the illustratedembodiment the data is transferred indirectly from the option system 12to the display driver 20, it is possible to transfer the data directly,if so required.

FIG. 3 is an example of a simplified block diagram of the circuitry ofthe standard timekeeping system 10 shown in FIG. 1. The circuitrycomprises a standard frequency oscillator 14, a frequency synthesizer16, a control unit 30, a timekeeping register 32, an alarm unit 34, adata modulating unit 36, external control devices 38, level shiftercircuits 40, a bit serial-to-parallel converter 42, a decoder 44, a wordserial-to-parallel converter 46, a display driver 20 and a display 22.

The standard frequency oscillator circuit 14 is crystal controlled, andgenerates a frequency of 32,768 Hz. This is applied to frequencyconverter 16, which generates the 256 Hz timekeeping input frequency andvarious timing signals for the standard timekeeping system. This 256 Hzsignal is input to an adder circuit in the timekeeping register 32, soas to regularly update the current time data stored in this register.

The timekeeping register 32 is basically a storage register into whichdata can be added serially and into which initial values of time datacan be readily set.

The control unit 30 permits initial values of data, from externalcontrol devices 38 to be set into the storage register in thetimekeeping register 32.

The output data from the timekeeping register 32 is transferred to adata modulation unit 36, which varies the input to the display inaccordance with the data stored in the timekeeping register 32 and datawhich is input from the external control devices 38. The data modulatorunit also serves to periodically interrupt the flow of data to thedisplay driving circuits for saving current consumption. The latterconsists of level shifter circuits 40, bit serial-parallel converter 42,decoder 44, word serial-parallel converter 46 and display driver 20. Thefunction of the level shifter 40 is to increase the voltage level of thesignals from the logic circuits. The bit serial-parallel converter 42comprises a 3-bit shift register, which converts the output data bitsfrom serial-to-parallel mode. The output data thus converted is appliedto the decoder 44, which decodes the data for application to the displaydriver 20. The decoded display segment data is transmitted by thedisplay driver output circuits to the display 22.

As shown in FIG. 3, the output data from the standard timekeeping systemcan be supplied to the option system 12 as shown by dotted line. Thelatter is designed such that it delivers various signals to thefrequency synthesizer 16 and the timekeeping register 32 of the standardtimekeeping system.

A detailed block diagram of the circuitry of the standard timekeepingsystem is shown in FIGS. 4A, 4B and 4C, in which like or correspondingparts are designated by the same reference numerals as those used inFIG. 3. As shown, the standard timing oscillator 14 is connected to andcontrolled by a quartz crystal 48, to produce an output signal φ_(o),i.e., a pulse train with a repetition frequency of 32,768 Hz and a veryhigh degree of frequency stability. This is applied to one input of afrequency summing gate 50 in the frequency converter 16. Frequencysumming gate 50 has another input, to which a gain/loss adjusting signalcan be applied via frequency summing gate 52. One input of gate 52 isusually grounded, the other input being connected to the option system12 to receive the gain/loss adjusting signal. This is at a relativelylow frequency. The output signal φ_(z) from frequency summing gate 50 isapplied to the first timing pulse generator 54 in the frequencycynthesizer 16.

The first timing pulse generator 54 generates varous timing signals,including clock pulses φ₁ and φ₂, bit timing pulses T₁ to T₈ and, wordtiming pulses D₁ to D₁₆ as well as the signals φ_(UC1) and φ_(UC2) whichare utilized in timing pulse regeneration, and also may be used in avoltage booster circuit in the option system 12. A second timing pulsegenerator 56 in the frequency converter 16 receives timing signals fromthe first timing pulse generator 54 and generates various combinedtiming pulses. These include the timekeeping input signal D₁ T₁, of 256Hz, which is applied to the timekeeping register 32 as signal X.Timekeeping register 32 contains a shift register 58, in which thevarious types of data are stored. Shift register 58 has its output datafed back to its input, to form a ring configuration. It comprises afirst shift register 60, a serial adder circuit 62, a second shiftregister 64, an inhibitting gate 66, and an OR gate 68, all of which areconnected in series, with the output of the OR gate connected to theinput of shift register 60 to complete the ring. Shift registers 60 and64 have 60 and 4 bits respectively, to store timekeeping and other data.The serial adder 62 consists of an adder circuit 62a, a delay stage 62band an OR gate 62c.

Outputs Q62, Q63, Q64 and Q65 of the shift register ring 58 areconnected in parallel to data detecting unit 70, consisting of carry-outdemand detector 72 and data detector 74. The carry-out demand detector72 serves to detect those data conditions under which a carry operationmust be performed, and generates carry-out demand signals W3, W4 and W5,which are supplied to control unit 30, and gated through a carry inhibitgate to produce output X. This is input to the OR gate of the serialadder 62 to perform the carry function.

Data detector 74 monitors the data stored in shift register ring 58, andgenerates output signals ATO, O-sup, CONTA, and B, depending on the datacontents. Output signal O-sup indicates whether the tens digit of thedate stored in the shift register ring is zero, and is supplied to thedata modulation unit 36. Output signal CONTA indicates that the currenttime data of 1/16 seconds, stored in the shift register ring 58 has beenincremented, and is supplied to the data modulation unit 36, to time theoutput of bursts of data and clock pulses from this unit. Output B isproduced by the changing of the current time data stored in the shiftregister ring 58, and is supplied to the data modulating unit 36 toactuate display flashing at a frequency of 1 Hz.

Control unit 30 receives input signals SH, SM, SK, SD, SUO, SUT, SU1 andSU2 from external control devices 38, and generates output signal S₁,S₂, U, UL, G, So and X. Output signals S₁ and S₂, and the invertedsignal UL are supplied to the alarm unit 34. Output signal X is suppliedto the timekeeping register 58 as described above. Output signals U, ULand G are supplied to the data modulating unit 36. Signals SD, SK ansSU2 which generate various signals within the control unit, also passfrom the control unit 30 to be applied to the data modulating unit 36.The output signal So from control unit 30 is supplied to the carry outdemand detector 72.

The data modulation unit 36 has several data switching functions. One isto modify selected portions of the serial data transferred to thedisplay device. Another function is to chop the flow of data and timingpulses to the display driver unit and option unit, so as to reduce powerdissipation in these circuits. To be more specific, a data choppingcircuit 76 in the data modulation unit sends out the data to bedisplayed, as a serial burst designated DATAOUT.sup.Δ, for a fixed timeperiod following the start of each cycle of the timekeeping input clock,i.e. every 1/256 seconds. In synchronism with each burst of data, thedata chopping circuit 76 also transmits bursts of timing pulses for thesame period, designated as T₈ Δ,φ₂ Δ, and φ₁ Δ, to the display drivercircuits and the option unit. This serves to significantly reduce powerconsumption.

As stated above, the data modulation unit also serves to select certainparts of the ouput data pulse train and modulates it so as to causeflashing of this data when it is displayed. In the application of thisinvention described herein, a linear scale type of analog, rather thandigital, display is shown to indicate either seconds time data or daysof the week. This analog type display, which consists of a number ofsegments arranged in line, may be modulated such that the indicatingsegment (showing, for example the day of the week) is switched "ON" andall other segments switched "OFF". The modulation mode may also,however, be such that the indicating segment is switched "OFF" and allother segments "ON". Changing the display mode in this way permits clearindication of which of more than two alternative kinds of data is beingshown by the analog display. Variation of this display mode is performedby the data modulation unit 36.

As has been stated, the technique of chopping the flow of data and clockpulses out of the data modulation unit results in a marked reduction inpower consumption. This chopping is performed at a repetition rate of 16Hz, and results in the power consumption of the display and drivercircuits being only 10% of that of the conventional standard dynamictimekeeping system. The functions performed by the present inventionhave, in the prior art, been only possible by using large scaleintegrated circuits consuming relatively high power. The presentinvention, therefore, makes possible the construction of wristwatcheshaving a similar multiplicity of functions to previous designs butconsuming less power, thereby enabling a battery of lower capacity andsmaller size to be used. It should be noted that with the presentinvention it is possible to arrange that data be transferred to thedisplay driver only when the contents of the data change, or to arrangethat the data only be displayed when required by the user. Theseexpedients can enable even greater reductions in power consumption to beachieved.

Outputs Q62, Q63 and Q65 of the shift register 64 are supplied to thedata modulation unit 36. Signals Q62 and Q63 are used in the datamodulating unit 36 to generate a 1 Hz signal φ₁ Hz, which actuatesflashing of parts of the display when required. Q65 is used ingenerating a signal which causes the daily alarm symbol to be displayed.The daily alarm is an alarm mode which, once set in, will cause anaudible or visual signal to be generated each day at the same time,until erased by the user. Signals B and O-SUP are also applied to thedata modulation unit 36. B is a multiplexed timing signal, also used ingenerating the flashing signal at 1 Hz. Signal O-SUP serves to suppressleading zeros of the date numeral. Signal F, delivered from the alarmunit 34, serves to initiate display flashing to indicate that alarm timecoincidence has taken place. Signals SD, SK, and UL are also applied tothe data modulation unit 36, and from these signals a signal D_(D) isproduced, which causes display of alarm time, date or current time,depending on how the external control members have been set by thewearer.

Signals SU1 and SU2 serve to input data to the standard timekeepingsystem, the components to which the data is supplied being selected bycombinations of input signals SH, SM, SK, SD and SUO or SUT provided byexternal control devices 38, which will be described later. Signals SUOand SUT permit the unlocking of input terminals to allow data to beinput. SUO is applied continuously while data is being inset, while SUTenables access to, i.e. "unlocking" of, data input circuits for a fixedtime duration after setting in of new time data begins. In the specificapplication of the present invention described hereafter, input SUO isnot utilized, and SUT is connected directly to SK.

Signals SH, SM, SK, SD, SUO and SUT, accordingly have the followingfunctions when applied to the control unit:

a. Selection of addresses to be unlocked. This is done by combinationsof input signals SH, SM, SD and SK.

b. Unlocking of the selected addresses, by SUO and/or SUT.

c. Allowing the input data, from SU1 and/or SU2 into the unlockedaddresses, to permit the stored current time, alarm time or date to bechanged.

It should be noted that there is a case in which when the secondsdisplay is set to zero by an external control device, the unlockingsignals by SUO and/or SUT are not utilized. The circuit is also arrangedso that none of the displayed numerals will be changed to a higher ordernumeral by a carry generated while setting in of data is being carriedout, for example the hours data is not effected when the minutes data isset by the wearer.

Referring now to the alarm unit 34, the alarm time data is stored in theshift register ring 58, having been set in dependence on the signals SH,SM, SK, SD, SUO, SUT,SU2 and SU1. Two different types of alarm time datamay be stored, namely temporary alarm times and daily alarm times. Inthe case of temporary alarm times, the alarm time data is automaticallyerased from the storage register after an alarm warning signal has beengenerated, by means of a signal designated "erase". Access to alarm unit34 is initiated by the inverted signal UL. The circuit is arranged suchthat during the setting of the alarm time, alarm unit 34 is inhibitedfrom delivering an erase signal to the timekeeping register 32. Thealarm unit 34 is also arranged such that if the current time coincideswith the alarm time during the setting of the current time or setting ofalarm time, no erase signal is generated and no alarm signals areactuated.

Coincidence between the current time data stored in the shift registerring 58 and the alarm time data is detected by comparing during apredetermined time interval between timings D₆ and D₉ T₄ a data outputdesignated DATA 60, which is the DATA input to the 60th stage of theshift register ring 58, and a data output Q29 which is the output of the29th stage of the shift register ring, and is also designated as DATA28. Upon detection of a concidence, the alarm unit 34 sends an alarmsignal ALS to an alarm sound generating device 78, which remainsenergized for a predetermined time interval, e.i., one minute. Duringthis time interval, the alarm unit 34 sends a signal F to the datamodulating unit 36, whereupon unit 36 generates an output signal whichcauses almost all of the display elements to flash. When the weareracknowledges the alarm and depresses a switch connected to the inputsignals SU1 or SU2, the flashing of the display and the alarm sound arecaused to be stopped. Switch 80 is for inhibiting the alarm operation.

As stated previously, shift register ring 58 is so arranged as to storeeither temporary alarm data or daily alarm data. If temporary alarm datais stored alarm indication is initiated only once, then the alarm unit34 delivers a signal designated "erase" to the shift register ring 58.This causes erasure of the stored alarm data. If daily alarm data isstored in the shift register ring 58, the erase signal is not generatedby alarm unit 34. The alarm time data stored in the shift register ring58 may also be erased by the wearer setting the hours digit of the alarmtime to zero, using external control members 38. The "0" state of thealarm time is detected by the data detector 74, which consequentlygenerates a signal ATO. This indicates that the alarm time is in the "0"state. This signal is applied to the alarming unit 34, causing an erasesignal to be generated. When the "alarm time zero" condition isdisplayed, a zero appears in the hours digit and the minutes digits areblanked out.

Indicated as 82 is a circuit which can be used to provide additionalfunctions in the electronic timepieces and is referred to herein as aflexible circuit. In this example, a bistable circuit in the flexiblecircuit is arranged to provide frequency division and thereby generate asignal LY, indicating a leap year, which is supplied to the datadetecting unit 70.

FIG. 5 shows an example of the time standard signal oscillator 14 andcircuit elements associated therewith. As shown, the standard timingoscillator 14 comprises a quartz cyrstal vibrator 48, operating at afrequency of 32,768 Hz, a CMOS inverter 90, a resistor 92 having aresistance of about 30 Megohms, and a resistor 94 having a resistance ofapproximately 500 Kohms. The latter serves to maintain the outputimpedance of the inverter 90 at a substantially constant level, therebyensuring low distortion of the waveform from the inverter 90 to thevibrator 48. The oscillator circuit also contains a capacitor 96 havinga capacitance of about 25 pF and a trimming capacitor 95 having acapacitance of about 20 pF. The quartz crystal 48 has a resonancefrequency of, for example, 32,768 Hz. The exclusive OR gate 50 serves toproduce a signal φ₂ having a frequency equal to the sum of thefrequencies of two signals φ_(N) and φ_(O) applied to its inputs. Sincethe output frequency will not be varied by the logical negation of theoutput from exclusive OR gate 50, an identity gate may also be used toaccomplish the same purpose.

FIG. 6 shows the waveforms of the input signals φ_(N) and φ_(O) and theoutput signal φ_(Z). It will be seen that the output signal φ_(Z) isobtained when the signals φ_(O) and φ_(N) are applied to the inputterminals of the exclusive OR gate circuit 50 and has a frequency equalto the sum of the frequencies of the signals φ_(O) and φ_(N).

FIGS. 7A and 7B show circuitry details of an example of the synthesizer16 shown in FIG. 3 and FIG. 4A. As shown, the output signal φ_(Z) fromthe frequency summing gate 50 is applied to a 2:1 frequency divider 100forming part of the first timing pulse generator 54, comprising abistable circuit 102 and AND gates 104 and 106. The 1/2 frequencydivider 100 thus constituted generates clock pulses φ₁ and φ₂ which areapplied to the timekeeping register 32, data modulating unit 36, displaydriver 20, etc. for purposes to be described later in detail. The clockpulses φ₂ are also applied to a 4:1 frequency divider 108, comprisingfour cascade-connected shift register stages 110, 112, 114 and 116 whichare connected in a loop through a logic gate 118. The 1/4 frequencydivider 108 generates bit timing pulses T₁, T₂, T₄ and T₈ which areshown in FIG. 8. Each of these bit timing pulses has a repetitionfrequency of one quarter the frequency of the clock pulses φ₂ and apulse width equal to the period of clock pulses φ₂. The rising edge ofthese bit timing pulses are synchronized with the rising edges of theclock pulses φ₂, and they differ in phase by an amount equal to theperiod of the clock pulses φ₂. These timing pulses are delivered to thesecond timing pulse generator 56, which generates various combinedtiming signals. Timing pulse T₈ is also delivered to the data modulatingunit 36, for a purpose to be described later in detail. Timing pulse T₁is delivered to a 1/16 frequency divider 120, comprising eight latchcircuits 122 through 136 and a bistable circuit 138. The latter circuitis of the toggle type and its output Q138 rises and falls in synchronismwith the timing pulse T₁, and has a period twice that of the timingpulse T₁. The output of bistable circuit 138 has the same waveform asthat of clock pulses φ_(UC1). The relationship between signals Q138 andφ_(UC1) will be clearly seen by referring to the waveform thereof shownin FIG. 9, which shows the waveforms of the various timing signals. ANDgates 140 and 142 connected to bistable circuit 138 generate clockpulses φ_(a) in response to the rising edge of clock pulses φ_(UC1) andclock pulses φ_(b) in response to the falling edge of clock pulsesφ_(UC1), as shown in FIG. 10.

The signal φ_(a), φ_(b) and T₁ are related as follows:

    φ.sub.a +φ.sub.b =T.sub.1

    φ.sub.a ·φ.sub.b =0

(corresponding to the low level "L")

    φ.sub.a ·T.sub.1 =φ.sub.a

    φ.sub.b ·T.sub.1 =φ.sub.b

Clock pulses φ_(a) and φ_(b) are generated in order to minimize thedivider 120 which generates 16 word timing pulses D₁ through D₁₆. InFIGS. 7A and 7B, the 4:1 divider 108 is comprised of the four data typebistable circuits 110, 112, 114 and 116, triggered by clock pulses φ₂.If the 16:1 divider 120 were designed using components similar to thoseused in 4:1 divider 108, it would be necessary to provide 16master-slave data type bistables in order to generate the 16 word timingpulses. In the illustrated example of FIGS. 7A and 7B, however, the 16:1divider 120 is comprised of only eight latch circuits, functioning asfour master-slave type bistables.

A data input signal is read into the latch circuit 122 by the risingedge of clock pulse φ_(a), generating output Q122. Circuit 122 remainslatched after the clock pulse φ_(a) returns to the low level. Before theclock pulse φ_(a) again goes high output Q122 is latched into circuit124 by clock pulse φ_(b). In this manner, the data passes throughsuccessive latch circuits and each time the data passes through onelatch circuit it is delayed by one period of timing pulse T₁. Theoutputs Q124 and Q132 are gated through a mode lock gate 144, the outputof which is connected to a NOR gate 146 together with the output Q128.In this manner, the latch circuits 122 to 136 generate signals Q122 to136, each with a period 16 times that of T₁ and 50% duty cycle. Thedigit pulses D₁ to D₁₆ are generated using the output signals of latchcircuits 122 to 136 respectively. For example, digit pulse D₁ isgenerated by gate 148 from the inverted signals Q122 and Q136. Likewise,digit pulse D₂ is generated by gate 150 from inverted signals Q124 andsignal Q122. The other digit pulses D₃ and D₁₆ are generated in asimilar manner and, therefore, a detail description is herein omitted.

FIG. 8 shows the relationship between the clock pulses φ_(Z), φ₂ and φ₁and the timing pulses T₁, T₂, T₄ and T₈ generated by the 4:1 divider 108of FIG. 6A. FIG. 9 illustrates the waveforms of the bit timing pulses T₁to T₈, word timing pulses D₁ to D₁₆, data signal DATA and pulses φ_(UC1)and φ_(UC2). Indicated as P in FIG. 9 is the data appearing at output Q1of the shift register ring 58 at word times D₁ to D₁₆. The relationshipbetween the word timing pulses and the data is as follows:

    ______________________________________                                        D.sub.1 :       1/256 second word                                             D.sub.2 :       1/16 second word                                              D.sub.3 :       1  second word                                                D.sub.16 :      alarm time symbol word                                        ______________________________________                                    

The value of the data corresponding to each word time is given by thewaveform appearing at output Q1 of shift register ring 58 for each ofthe bit times T₁, T₂, T₄ and T₈ of that particular word. The data isweighted at these four bit times as follows. Bit T₁ corresponds to theleast significant weight, a high level of data at T₁ corresponding to"1" and a low level to "0". High levels of data at times T₂, T₄ and T₈represent the weights 2, 4 and 8, respectively. From this it can be seenthat the waveform of the data signal appearing at the shift register 58outputs represents the content thereof. The data waveforms shown in FIG.9 indicate that the standard timekeeping system is registering a currenttime of 2:32 PM, 33 and 1/16 seconds plus 8/256 seconds, on July 24 andthat a daily alarm time of 11:59 AM has been set in.

The clock pulses φ₁, φ₂, bit timing pulses T₁, T₂, T₄ and T₈ and wordtiming pulses D₁ are also supplied to the second timing pulse generator56, by which various combined timing signals are generated. To simplifythe illustrations, a detail circuit arrangement of the second timingpulse generator 56 is herein omitted.

FIGS. 11A and 11B show a circuit diagram of an example of thetimekeeping register 32. As described above, the timekeeping registercomprises a shift register ring 58 and a data detecting unit 70, whichincludes a carry out demand detector 72 and a data detector 74.

The shift register ring 58 includes a 60-bit shift register 60, theoutput Q1 thereof being coupled to a four bit shift register 64 via aserial adder circuit 62. The output Q61 from shift register 58 isconnected to one input of an AND gate 66 and the output of this gatecircuit is connected to one input of an OR gate 68. The other input ofAND gate 66 is connected to the output of an OR gate 162 through aninverter 160. As a consequence, the output from AND gate 166 will be atthe "L" level whenever the output of OR gate 162 is "H". The output fromOR gate 68 is fed back to the input of shift register 60 as data D60,and also sent to the data modulating unit 36 and to the alarm unit 34for various purposes to be described later.

The shift registers 60 and 64 are arranged such that data is latchedinto each shift register stage when clock pulses φ₁ goes to the "H"level, and appear at the output of the stage when the clock pulse φ₂goes "H".

The clock pulses φ₁ and φ₂ have a frequency of 2¹⁴ Hz so that writing inand reading out of data is performed 16,384 times per second, i.e. thedata is shifted through the registers at this frequency.

As already described, a serial adder 62 is included in the shiftregister ring 58 so that data stored therein may be incremented. Theserial adder 62 comprises a half-adder 62a, bistable delay stage 62b, anOR gate 62c, and has an α input to which the data from shift register 60is applied, and a β input which receives the output of gate 62c. The"sum" output of the adder, designated S, is connected to the D input ofbistable 64d, and a "bit carry" output, designated C connected to theinput of shift register 62b.

The signal X applied to gate 62c of the adder 62 is used to add invarious kinds of data to the shift register contents, including wordcarry inputs, a time setting input and a time unit input D₁ T₁. Sincethe 64 bit shift register ring 58 successively transfers the data inresponse to clock pulses at a frequency of 256×16×4=16,384 Hz, a datainput of "1", after being initially input at time D₁ T₁ will thereafterappear at input α of the adder 62a at a timing of D₁ T₁ every 1/256seconds. The carry bit signal C is delayed in stage 62b by one bit time.Thus it is applied to input β of the adder 62a, at timing D₂ T₂. Signalsappearing on outputs S and C are expressed by the following equations:

    S=α·β,

    C=αβ=αβ

The avoid confusion and aid better understanding of the invention, thefollowing definitions and descriptions of the terms used herein will nowgiven.

i. Write-in and Readout:

As described above, when data is latched into the master stage of amaster-slave type bistable, this is termed "write-in". When this samedata appears at the slave stage of the output of the bistable, this istermed "readout".

ii. Shift Register:

The term "shift register" is used herein to mean an array of data typemaster-slave bistables connected in cascades. The terms "register" aloneis not limited to a shift register but applies to any system capable ofregistering data.

iii. Timing:

Signals appearing on the output terminals of the shift register stagesdiffer in timing by a factor depending on the clock pulse frequency.Since the clock pulses have a constant frequency, it is possible toconsider the output signals of the shift registers as a functions oftime. The output of any one stage of shift register 60 can berepresented by the symbol "DATA" (x, t), which is a function of theposition x of the output in the shift register configuration, and thetime t. The time t is herein referred to as a "timing". According tothis invention, the output data from the shift register ring 58 isperiodically transmitted in bursts before being delivered to the displaydriver and the option system. For these bursts of data, it is notstrictly correct to define the data as a function of time, since it isreally a function of the periodic bursts of clock pulses. But in thisspecification, the term "timing" is used according to the customs of theart. Accordingly, for example the signal D₁ T₈ φ₁ generated in theoption unit is also referred to by the term "timing".

iv. Data:

Where data which has been stored in the shift register ring 58 inresponse to the clock pulses is read out from any output terminal of theshift register, it is herein termed "data". The number 60 of the outputdesignation DATA 60 indicated the number of the shift register stage towhose input this data signal is applied. I.e. data 60 comes from theoutput of shift register stage 61, in FIG. 11A. Sometimes DATA (x.t) isabbreviated to "DATA x" or "t DATA" in which x following the term DATAmeans that the data is connected to the x-th data input of the shiftregister. Further, the designation D₁₆ DATA 60 means the DATA 60 outputat word timing D₁₆ and, especially, X-DATA-64 is simply represented as Xdata. The x-th output of the shift registers is expressed as Qx, thusDATA 60 corresponds to Q59. In other words, the 59th output of the shiftregister is connected to the 60th data input terminal of the shiftregister.

The way in which data in the shift register ring 58 is incremented sothat counting is performed will now be described, reference to the 1/256second word time data as an example.

As previously stated, the 1/256 second word is incremented once percirculation of the shift register ring 58. This is done by adding in thetime unit signal of D₁ T₁, i.e. by applying an "H" logic level to the xinput of NOR gate 62c of the adder circuit at timing D₁ T₁. Consider ashift register circulation, when the 1/256 second word has the valuezero, so that at timings D₁ T₁, D₁ T₂, D₁ T₄ and D₁ T₈ only low logiclevels will be applied to the input α of the adder. Since an "H" logiclevel is applied to the β input of the adder at D₁ T₁ by the time unitsignal, then during the following circulation the 1/256 second word willhave the value "one". So that at the next timing D₁ T₁, an "H" levelwill be applied to both the α and β inputs of the adder. This will causea "L" at the S output and an "H" at the C output of the adder, and afterone bit delay, i.e. at digit time D₁ T₂, this will appear at the inputof NOR gate 62c and hence at the β input of the adder. Thus one bit isadded into the shift register at timing D₁ T₂, and since this has aweight of 2, the 1/256 second word now has the value 2. At the nexttimings D₁ T₁, D₁ T₂, D₁ T₄ and D₁ T₈, the output from shift registerstage Q1 to the adder will be the sequence "0", "1", "0", "0". And whenthese timings next occur, the sequence will be "1", "1", "0", "0",corresponding to data value 3. This corresponds to a time of1/256+2/256=3/256 seconds. This will continue until the sequence "1","1" , "1", "1" appear during word timing D₁. When this is applied to theadder, together with the time unit signal, carries are generatedresulting in the sequence "0", "0", "0", "0", "1" at timings D₁ T₁, D₁T₂, D₁ T₄, D₁ T₈ and D₂ T₁ being output from the S terminal of theadder. The 1/256 word now has the value 0 and the 1/16 second word thevalue 1. The 1/16 second word will then be subsequently incremented inthe same way as the 1/256 second data, but only every 1/16 seconds.

The four bits of D₂ data are thereby varied at 1/16 sec., 2/16 sec.,4/16 sec. and 8/16 sec. respectively.

In this manner, the shifts register ring 58 serves both to store 16words of 4 bit data and also to increment 12 words so as to continuallyupdate the current time stored therein. For example, the data 64designated by the timing D₃ T₁ to D₃ T₈ is incremented once everysecond, and D₃ represents one seconds' word.

The arrangements for performing the carry function between the differenttime units in a timepiece are dictated by the maximum values of the"units" and "tens" digit words corresponding to minutes, hours, etc.

For seconds and minutes, the "units" digits of the corresponding dataare in the range 0 to 9, and the "tens" digits from 0 to 6.

For hours and months, the "units" digit ranges from 1 to 2, for weeks ofthe days there is only a "units" digit, from 1 to 7. Means musttherefore be provided for detecting when a word carry or digit carry isnecessary, dependent on these "units" and "tens" values, i.e. after the"tens" of the minutes data reaches 6, a word carry must be generated toincrement the hours data, when the next minutes data increment occurs.

For example, the four bits of D₃ data, respectively, represent the 1/1sec., 2/1 sec., 4/1 sec. and 8/1 sec. weights of the one second "units"data, so that when the D₃ data goes to the binary state "0" "1" "0" "1",10 seconds is represented. In this case, it is necessary to reset thefour bits of D₃ data to "0" "0" "0" "0" and carry to the 10 second bitof the D₄ data, which represents the "tens" of the seconds data. Thus ifthe four bits of D₄ data are "0" "0" "1" "0", the carry will change themto "1" "0" "1" "0". In other words, the carry out operation is performedby: (a) simultaneously examining the count states of the four bits of adata word, (b) detecting whether a carry must be generated, (c)converting the count of the word to an initial count of the word, and(d) adding "1" to the succeeding word in the following bit time.

In the embodiment of this invention shown in FIGS. 11A and 11B the datafrom outputs Q62, Q63, Q64 and Q65 of shift register ring 58 aremonitored by a data detecting unit 70 and carries are generated independence on the contents of these outputs.

It should be noted that, at the bit time of T₈ of the data word beingmonitored, the outputs Q62, Q63, Q64 and Q65 (=DATA 64) will,respectively, represent the bit weights "1", "2", "4" and "8" of thedata, respectively.

As previously mentioned, the data detecting unit 70 comprises a carryout demand detector 72 and a data detector 74, which generate variousoutput signals required by the control unit of this invention andmonitor the data circulating in the shift register ring 58.

The carry out demand detector 72 comprises matrix gate circuits 166,168, 170, 172 and 174, which are connected to the output of bistables64a, 64b, 64c and 64d of shift register 64, respectively. The logicrelationships for inputs and outputs of these matrix gate circuits areshown in the diagram on the left hand side of FIG. 11B as E. Referringnow to matrix gate circuit 166, and noting that inverted signals Q65,Q64, Q63 and Q62 are also provided (although all of the signals are notused in gate circuit 166), it will be seen that a gate output will begenerated under the logic condition D15.Q65.Q64.Q62+D15.Q65.Q64.Q63.Since pulse D15 goes high as the alarm time hours word data bits beginsto shift through register stages 64, 63, 62 and 61, it will be seen thata gate output will be generated for alarm time hours counts of 13, 14 or15 at the timing of D₁₅ T₈.

The output is passed through a delay circuit 180 (see FIG. 14 fordetails of this circuit) where it is delayed by one bit time andpersisted one word time. The resultant output, as time D₁₆ is signal W1,and because of the delay circuit 180 this signal has a duration of oneword time.

Note that a word carry signal is not generated when the alarm time hoursdata is in the "13"˜"15" state and "0" hour state is settable. This isfor the wearer to be able to set hours data to zero, for reasonsexplained later. W1 is applied through OR gate 162 and inverter 160 tothe input of AND gate 66 thereby inhibits gate 66 while the alarm timehours data is applied to it. This sets the alarm time hours data tozero, i.e. erases the data.

Matrix circuit 168 generates an output "H" for counts of the days ofweek data of zero, eight or more than eight. This is output at the endof word time D9. Gate 168 also generates an output "H" for counts ofzero, 13, 14 or 15 of the current time hours data and the months data,at times T8 of word pulses D7 and D12 respectively. As for gate 168described above, the output is delayed and extended in circuit 180, tobecome output W₂. W₂ is applied through OR gate 162 and inverter 160 tothe input of AND gate 66. Having been inverted to logic "L" state, itinhibits gate 66 while the data which has caused generation of W₂ isentering, thereby erasing this data. W₂ is also applied to OR gate 182,whose output is "ANDED" with bit timing signal T₁. The output of gate184 is sent through OR gates 186 and 68 into the timekeeping register,so that a data count "one" has been set in. The word carry output formonths data, which of course normally occurs once per year, is gatedthrough AND gate 188 by pulse D₁₃, and is then available for connectionto a leap year counter circuit if this is incorporated.

The matrix gate circuit 170 serves to detect the count "4" of the "tens"of days data and the count "6" of the "tens" of minutes data, "tens" ofsecond data of current time, also "tens" of minutes data of the alarmtime, actuated by word pulses D₁₁, D₄, D₆ and d₁₄ respectively. Gatecircuit 170 also detects the count "10" of the "units" of seconds data,"units" of minutes data, "units" of days data for current time and"units" of minutes data of the alarm time, in response to the wordpulses D₃, D₅, D₁₀ and D₁₃ respectively. This gate circuit also detectsthe count "2" of the AM/PM symbol data actuated by the word pulse D₈. Anoutput signal W₃ is generated thereby which is used to erase the dataproducing it, and to generate a carry into the next word. The outputsignal W.sub. 3 is aplied through OR gate 162 and inverter 160 to effecterasing. At the same time, signal W₃ is applied to the control unit,thereby generating an output x, which is applied to adding circuit 62 ofthe shift register ring 58 thus effecting a carry into the succeedingword time data.

Signal W₃ is also applied to one input of AND gate 190, to whose otherinput the word pulsed D₉ is applied. The output of gate 190 is appliedto OR gate 192, whose output is delayed by one word time by delaybistable 180. Output signal W₄ from this delay unit causes a carry intothe days data each time the "PM" symbol changes to "AM" at midnight.

The matrix gate circuit 172 stores the information that count "11" ofthe hours data of alarm time has been set, by writing an output into astorage latch at word time D₁₅ T₈ φ₁. The output of this latch isconnected back into matrix gate circuit 172 so that a transition fromcount "11" to count "12", occurring during a subsequent memory cycle,generates an output signal. This is applied to OR gate 192 to produceoutput signal W₄, used to carry into the AM/PM data word.

If a seconds zeroing signal So is applied to matrix gate circuit 174when the "tens" of the seconds data has the count "3", "4" or "5", thena carry (W₄) is generated into the succeeding minutes data. At the sametime signal So is input to OR gate 162, thereby setting the seconds datafrom 1/256 seconds digit to 10 seconds digit.

The matrix gate circuit 176 detects long and short months producing anoutput signal W₅ which controls the "units" of days data, "tens" of daysdata and "tens" of months data. Matrix gate circuit 176 is alsoconnected to latch circuits 194, 196, 198 and 200, which detect andstore the data regarding February, 20 days, 30 days and inverted signalsof the short months (Feb., Apr., Jun., Sept., and Nov.). The conditionswhich are detected to generate a word carry to change the diaplay to the1st of the succeeding month are:

(i) Feb. 29th, in a normal (not leap) year.

(ii) Feb. 30th, or counts higher than 30.

(iii) The 31st day count of the short months.

(iv) The 32nd day count and more of both the long and short months.

The results of the above items i, ii, iii and iv are OR'd to produce anoutput signal W₅.

Signal W₅ is used as a carry signal to effect carrying to the next digitafter the data producing it has been reset to zero. If, for some reason,a count of 31 occurs for February, the signal W₅ applies a carry to the"tens" of the days data, so that Feb. 31 converted to Feb. 41. The"tens" of days data is thereby, in effect, reset to zero (since a countof more than 3 has no significance) and a carry signal is applied to themonth data. Thus, March 1st is displayed.

In the case of months of 30 days, "short months", the following sequenceoccurs:

a. The status of "not short month" is detected and stored in latch 200,by pulse D₁₂ T₈ φ₁.

b. This latch output is inverted and applied to matrix gate 176 as aninput labelled "short month".

c. The count of 30 date days is detected and stored in latch circuit198. The output of this latch is applied to matrix gate 176 labelled as"30 days".

d. The transition from 30 days to 31 days is detected by the matrixgate, and generates an output W₅. This is applied to the carry input NORgate of the control unit in FIG. 12, causing an increment of the "tens"digit of date days to 4.

As explained above, as well as causing a "months" carry, this isequivalent to setting this date days data to zero. W₅ is also applied togates 162 and 82 of the timekeeping register 32 in resister 58, causingthe "units" of date days to be set to a count of one. The result of theabove sequence is that the date data at midnight at the end of a "shortmonth" is changed to the 1st day of the following month. Whenever acount of 32 to 39, inclusive, is detected (by the OR gate output at thebottom of FIG. 11B in the matrix gate), a W₅ output is generated and thedate data is thereby set to the 1st of the following month, in the sameway as described above for the "short" months. This covers the case ofmonths of 31 days, as well as any spurious states due to noise pickup orwhen power is first applied to the timepiece.

In the case of February, the two inverting buffers shown on the left ofFIG. 11B with inputs U and LY enable adjustment to be made for leapyears. Normally, the inputs to both these inverters are low. In thiscase, the state of "Feb. 28" is detected and stored in the latch circuiton the left of these inverters. Then when the transition to Feb. 29occurs, a W₅ output is generated to produce a date of Mar. 1, asdescribed above. However, in the event of a leap year, then the input tothe latch circuit can be inhibited, either by the output of a counterwhich generates an output LY when a leap year occurs, or by the wearermanually setting the date to Feb. 29. The latter procedure is possiblesince the action of setting a date causes signal U to be generated.

Data detector 74 comprises a matrix gate circuit 202, which detects thecount "0" in the 1/16 sec. data, "units" of seconds data, "tens" ofseconds data and "units" of minutes data, during word pulses D₁, D₂, D₃and D₄ respectively. This output signal of the detector is delayed byone bit time by delay circuit 180, thus producing a signal [B], which isused as a composit synchronizing signal. [B] is also used in generatingreset signals for a timer circuit in the control unit, and various logiclevel setting circuits. These control the logic levels of all inputterminals connected to external switches. Signal [B] is also used toproduce 1 Hz switching signals in the data modulation unit, which serveto cause flashing of all or parts of the displayed data. The logicalproduct B·D₅ of signal [B] and the word pulse D₅ gives a signal of oneminute period, and the logical product B·D₄ ← gives a signal of 10seconds period.

Actuated by word pulse D₁₁, the matrix gate circuit 203 detects thecount "0" of the "tens" of days data, and generates an output signal[0-SUP] to suppress display of this "0". Display of leading zeroes inthe seconds and minutes display is acceptable, but it is desirable tosuppress them in the case of the days display. Unsuppressed display ofleading zeroes for the seconds and minutes data seems natural, and helpsto present misreading of the display. However, it should be noted thatmodifications may be made to the circuit arrangement to suppress displayof the count "0" in any desired digit. The signal [0-SUP] is deliveredto the data modulating unit to actuate suppression of the "0" display ofthe "tens" of days data.

The matrix gate circuit 205 detects count "0" of the 1/256 second data,its output signal being delayed by one bit time in delay bistable 205 togenerate an output signal [CONTA].

Matrix gate circuit 205 is also connected to a latch circuit 204, whichdetects the count "0" of the hours digit of the alarm time in responseto timing pulse D₁₅ T₈ φ₁, producing an output signal [ATO] whichindicates that the alarm time hours data is zero, i.e. that no alarmtime is set in.

The matrix gate circuit 206 detects the bit with weight 2² of the 1/256second digit, i.e., output Q64 of bistable 64. Output Q64 is read out bylatch circuit 207 at following time pulse D₁ T₈ φ₁. This output is a 32Hz signal, used for driving display elements.

An AT-ERASE signal is applied to the OR gate 162 from the alarm unitwhen the current time and the alarm time coincide, if a temporary alarmhas been set in. The AT-ERASE signal casues an inhibit to be applied togate 66, thereby setting the stored alarm time data to zero.

Table I shows the relationship between the word pulse D₁ through D₁₆ andthe outputs W₁ through W₅ from the data detecting unit 72. In Table I,the symbol * means that a carry is made from the "units" of days data tothe "tens" of days data, and a carry is made from the days data to themonth data at the end day of the month. In this case, the data which hasgenerated a carry is set to "1" after the carry is performed. The symbol** means that a carry is effected into the weekday data. The symbol ***means that the transition from count "11" to "12" of the hours data isdetected and a carry is made into the next data word, which is the AM/PMsymbol data. A symbol "-" means that no, W output signal is generated.

                                      TABLE I                                     __________________________________________________________________________                                       Output Z; set-                                                                        Word                                                   Data word to                                                                         Output Y; set-                                                                        ting "1" into                                                                         Output X;                          Data         Count  which carry                                                                          ting previous                                                                         data after                                                                            to                                 Date  monitored                                                                            Min.                                                                             Max.                                                                              is made                                                                              data to zero                                                                          reset to zero                                                                         next word                                                                            Output                      __________________________________________________________________________    1/256 sec.                                                                          D.sub.1                                                                              0  15  D.sub.2                                                                              not necessary                                                                         not necessary                                                                         not necessary                                                                        --                          1/16 sec.                                                                           D.sub.2                                                                              0  15  D.sub.3                                                                              "       "       "      --                          1 sec.                                                                              D.sub.3                                                                              0  9   D.sub.4                                                                              necessary                                                                             "       necessary                                                                            W.sub.3                     10 sec.                                                                             D.sub.4                                                                              0  5   D.sub.5                                                                              "       "       "      "                           1 min.                                                                              D.sub.5                                                                              0  9   D.sub.6                                                                              "       "       "      "                           10 min.                                                                             D.sub.6                                                                              0  5   D.sub.7                                                                              "       "       "      "                                                                             ***                         hour  D.sub.7                                                                              1  12  D.sub.8                                                                              "       necessary                                                                             ***necessary                                                                         W.sub.2, W.sub.4            PM    D.sub.8                                                                              0  1   D.sub.9, D.sub.10                                                                    "       not necessary                                                                         **necessary                                                                          W.sub.3                     week day                                                                            D.sub.9                                                                              1  7   none   "       necessary                                                                             not necessary                                                                        W.sub.2                     1 day D.sub.10                                                                             0  9   D.sub.11                                                                             "       not necessary                                                                         necessary                                                                            W.sub.3                     10 days                                                                             D.sub.11                                                                             0  3   D.sub.12                                                                             "       not necessary                                                                         necessary                                                                            W.sub.3                     month D.sub.12                                                                             1  12  (NY)   "       necessary                                                                             not necessary                                                                        W.sub.2                     AT-1 min.                                                                           D.sub.13                                                                             0  9   D.sub.14                                                                             "       not necessary                                                                         necessary                                                                            W.sub.3                     AT-10 min.                                                                          D.sub.14                                                                             0  5   no     "       "       not necessary                                                                        W.sub.3                     AT-hour                                                                             D.sub.15                                                                             0  12  D.sub.16                                                                             "       "       necessary                                                                            W.sub.1                     AT-PM D.sub.16                                                                             0  1   no     "       "       not necessary                                                                        --                          Date data                                                                           D.sub.10, D.sub.11, D.sub.12                                                         1  28˜31                                                                       D.sub.12                                                                             "       *necessary                                                                            *necessary                                                                           W.sub.5                     __________________________________________________________________________

The conditions for generating signals Y, Z, and X can be summarized asfollows:

1. Erasure of previous data: Y=W₃ +W₂ +W₁ +W₅ +S₀ +D₁ (T₂+T₄)+AT-ERASE+DATACL

2. "1" set into data after reset to zero: Z=(W₂ +W₅)T₁ +DATA IN

3. Carry to next data word:

    X={(D.sub.15 W.sub.3 +W.sub.4 +W.sub.5)·(Carry inhibit)+·D.sub.1 +S.sub.1 ·U{·T.sub.1 +{S.sub.2 '}

FIG. 13 shows an example of the "flexible" circuit 82. This is based ona bistable counter, and can be used to increase the versatility of thestandard timekeeping system of this invention. The output of gate 246 isnormally maintained at a high logic level, but is changed to a low levelfor a very short time period at a rate of 8 times per second by pulseB·D₂ ·T₈ ·Q62. During these low level intervals, bistables 208 and 210are preferentially set, so that both outputs go to "L" logic level. Ifinput FR is set to "H" level by grounding it gate 206 will present arelatively low resistance for the interval of pulse B·D₂ ·T₈ ·Q62.However, since this time period is short, the average current drawn whenthe output of 246 is grounded is less than 100 nA. If the output ofinverter 246 is left grounded, i.e., FR="H", bistables 208 and 210 canbe used for counting. Assuming that F_(A) ="L" and F_(B) = "L" at thecount of "0", the following relations hold:

    ______________________________________                                        at count 0     F.sub.B = "L"                                                                              F.sub.C = "L"                                     at count 1     F.sub.B = "H"                                                                              F.sub.C = "L"                                     at count 2     F.sub.B = "L"                                                                              F.sub.C = "H"                                     at count 3     F.sub.B = "H"                                                                              F.sub.C = "H"                                     ______________________________________                                    

Note that if terminal FR is not kept grounded, it may be used as thesource of an 8 Hz signal. If, however, the terminal FR is grounded,bistables 208 and 210 operate as binary counter. This "flexible" circuitmay be used to count leap years, since only a 4-bit counter is required.Although the setting of the counter to register leap years is sumewhattime-consuming, it is quite simple. The wearer can set the "leap year"condition by incrementing the months data manually, thereby causing aninput to the counter once every 12 months, and noting when the "days ofmonth" data for February advances to 29. The counter contents nowindicate a leap year.

FIG. 12 shows a preferred example of circuitry for the control unit 30.This unit is connected to a number of switch input terminals SH, SM, SK,SD, SUO, SUT, SU₁ and SU₂ and is actuated by input signals coming fromthese terminals to produce various control signals which are applied tothe timekeeping register 32 and the data modulating unit 36. SUO and SUTrepresent input terminals of electricl unlocking switches, which enablesetting of new time data into the timepiece, and SU₁ and SU₂ representdata input terminals for delivering the data inputs S₁ and S₂,respectively. The input terminals SH, SM, SK and SK are utilized tocontrol the storage locations to which input data is transferred. Eachof these input terminals is connected to a logic level setting circuit214, which maintains the input terminals normally at a logic level "L".When input terminal SH is at "H" level, data from input SI is read intodata words with a maximum count of 12. When SM="H", the data from inputSI is directed to data words with maximum counts of 60, 28, 29, 30 or31. When SD="H", data from input SI is directed to the date, month anddays of week data words.

Table II shows an example of the relationship between the signals fromthe switches SM, SH, SK and SD, and the resultant unlocking of variousdata storage locations and flashing of various parts of the displayeddata. The table is followed by an explanatory list of the abbreviationsused. For example, referring to the "time setting mode", it can be seenthat a combination of SH and SK high state signals, after unlockingsignal UL has been generated, will cause flashing of the display currenttime hours and updating of this data, i.e., new hours data is set intothe timepiece.

    TABLE II      SETTING MODE NORMAL OPERATING MODE  TIME SETTING MODE   DATE  N  DATE     DATE               DISPLAY O  DISPLAY  DISPLAY   (NO R  (WITH  (NO MK/     M/ H/   M/ H/ SWITCH SO MONTH) M  MONTH) SO MONTH) AT AT AT INH SO KT KT     INH DAY DATE MONT INH       SW. SM 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1     SET- SH 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1     TINGS SK 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1     IN SD 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1     UL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1     SU.sub.1 * * * * * * * * * * * * * * * * * * * * * 1 1 * * 1 1 * * 1 1 *      SU.sub.2 1 * * * * * * * * * * * * * * * 1 * * * 1 * * * 1 * * * 1 * *     *      ##STR1##      ##STR2##      ##STR3##

    ______________________________________                                        REMARKS:                                                                      NORM: Normal current time display                                             *: Either 1 or 0 (Don't care case)                                            So: Seconds zero setting                                                      Sw: Switch                                                                    UL: Data location is unlocked.                                                CI: Carry out inhibited                                                       IN: Signal generated within control unit due to switch signals.               U: Updating                                                                   fl: Flashing                                                                  SEC.: Seconds                                                                 MIN.: Minutes                                                                 H.: Hours                                                                     DAY: Days of the week                                                         DATE: Date of the month                                                       MONT.: Month                                                                  M/AT: Minutes of the alarm time                                               H/AT: Hours of the alarm time                                                 MK/AT: Alarm time daily/temporary symbols                                     INH: Input inhibited                                                          ALX: Connecting mark (for minutes/hours of a data alarm time)                 DD: Date mark (for date data of a date alarm time)                            "O": The counter is reset to zero, then continues                             counting from zero.                                                           1: High logic level                                                           0: Low logic level                                                            AM/PM: AM/PM condition indicating bit                                         ______________________________________                                    

As already noted, each of the input terminals SH, SM, SK, SD, SUO, SU₁and SU₂ is connected to a logic level setting circuit 214. This sets theterminal to a low logic level spontaneously when the correspondingswitch is released As shown in FIG. 15, the logical level settingcircuit 214 comprises an inverter 214a and a NOR gate 214b connected ina DC positive feedback loop. The input of inverter 214a is connected tothe output of NOR gate 214b and also to a switch input terminal, whileone input of NOR gate 214b is connected to the output of inverter 214aand the other to a timing pulse B·D₂ ·T₈ ·Q62. It is apparent that if alogic "H" signal is applied to the NOR gate input, its output willremain latched in the "L" state, and conversely, if a "H" level isapplied to the NOR gate output through low impedance, the output will beforced to be set in the "H" state. And in this state, since CMOS circuitelements are used, the output impedance presented by the NOR gate willbe high. In this example, a B·D₂ ·T₈ pulse having a width of 64 μsec. isapplied to the terminal every 1/16 second, setting the NOR gate outputto the low logic level. The low level output impedance is about 100kohms for CMOS elements. When the switch connected to the input terminalis depressed, the terminal is set to the high level. In this condition,the output of the NOR gate goes to the low impedance state every timethe pulse B·D₂ ·T₈ goes high. But due to the low duty cycle of thispulse, the current drain is extremely small, since the effectiveimpedance presented by the terminal will be of the order 100kΩ×1/16×10⁶/64≈100MΩ, when the corresponding switch is depressed. And the impedanceto ground when the switch is released is sufficiently low, about 100kohms, to greatly reduce interference pickup.

The switch input terminals SK, SD, SUO, SUT and SU₁ are connected to atimer 216. When a data unlocking command signal is applied to the timer216 from the input terminals, the timer produces an unlocking signal UL.When UL is in the "H" logic state, this releases an inhibit applied to agroup of matrix gate circuits, permitting data to be written intoselected data words. The input terminals SU₁ and SU₂ are connected todifferentiating circuits 218 and 220, respectively, which differentiatethe data input signals applied to the switch input terminals SU₁ and SU₂and generate the corresponding differentiated signals S₁ and S₂respectively, in dependence on the number of operations of the switches.The leading edges of signals S₁ and S₂ are coincident with the leadingedge of word pulse D₁, and each has pulse width equal to the repetitionperiod of word pulse D₁.

The input signals from terminals SH, SM, SK and SD and the unlockingsignal UL from timer 216 are applied to matrix gate circuits 222, 224,226 and 228. Matrix gate circuit 222 serves to select the data words tobe updated, in response to the word pulses and the signals deliveredfrom the input switch terminals. The word pulses D₄, D₆, D₉, D₁₁, D₁₂and D₁₄ select the minutes and hours data of the current time, date dataand month data and minutes and hours of the alarm time, respectively.

The minutes data of the current time is selected when the input suppliedto the gate circuit 222 is in a state in which SH·SM SK·SD·UL="H",generating an output designated U. This output signal is delayed by oneword time by a delay bistable 180 and applied to one input of AND gatecircuit 230. The differentiated signal S₁ is also applied to the ANDgate 230, enabling it to output a minutes data setting signal inresponse to the timing pulse T₁, which is supplied to OR gate 232,generating output signal X. The output X is applied to the addingcircuit 62 of the timekeeping register 32 to add "1" count to theminutes data.

Similarly, the hours data of the current time is selected whenSH·SM·SK·SD·UL="H". The date data is selected when SH·SM·SK·SD·UL="H".The month data is selected when SH·SM·SK·SD·UL="H". The minutes data ofthe alarm time is selected when SH·SM·SK·SD·UL="H". The hours data ofthe alarm time is selected when SH·SM·SK·SD·UL="H".

The gate circuit 224 produces a carry inhibit signal when time data isbeing set into the timepiece, generated by applying various inputsignals from the input terminals, unlock signal UL and word pulses D₉,D₁₀, D₇, D₁₂ and D₁₅ to it. The word pulses D₉ and D₁₀ correspond to thedays of week and the date data, respectively. In response to these wordpulses, gate circuit 224 produces output signals to inhibit a carry fromthe days of week data to the date data when the PM symbol is changed tothe AM symbol. The word pulse D₇ corresponds to the hours data of thecurrent time. In response to this D₇ pulse, gate circuit 224 generatesan output signal to inhibit a carry to the hours data when the minutesdigit of the current time is being set. The word pulse D₁₂ correspondsto the month data. In response to the word pulse D₁₂, gate circuit 224generates an output signal to inhibit a carry to the month data when thedate being set. The word pulse D₁₅ corresponds to the hours data of thealarm time. In response to the word pulse D₁₅, the gate circuit 224produces an output signal to inhibit a carry to the hours data of thealarm time when the minutes data of the alarm time is being set. Thecarry inhibit signals thus generated are applied to an inverter 234, sothat when the output of maxtrix gate 224 is "H", the AND gate 236 isinhibited. This prevents carry signals being applied to gate 232. Matrixgate circuit 226 generates an output which sets either a daily ortemporary alarm time condition, also an output signal which sets thedays of the week data. The timing pulse D₈ T₁ is used to set the days ofweek, and the timing pulse D₁₅ T₈ is used to set the alarm condition.

If input terminal SU₂ goes to "H" level, generating signal S₂, whenSH·SM·SK·SD·UL="H" or SH·SM·SK√SD·UL="H", then the gate circuit 226generates output signals which set the day or week or thedaily/temporary alarm time condition respectively. If input terminal SU₂goes to "H" level when SH·SM·SK·SD·UL="H", or SH·SM·SK·SD="H", thenmatrix gate 228 generates a signal which is delayed to become SO. Thissignal is applied to the input of gate 66 of timekeeping register 32, toperform the seconds zeroing function. FIG. 16 shows an example ofcircuitry for timer 216 utilized in control unit 30 of FIG. 12. Thistimer unit is arranged to be activated when input terminal SUT goes tothe "H" level. The output of OR gate 242 is applied to the set input offirst stage bistable 248, which is reset by one-minute signal B·D₅ T₈ φ₁or by input signal combination SD·SK. A second stage bistable 256 is setto "H" level after less than one-minute, when output Q of the firststage bistable 248 goes to "H". Output Q of 248, output Q of 256 andsignal SUO are applied to OR gate 260, which generates output signal UL,enabling data to be set into the control unit by signals S₁ and S₂. TheQ output of second stage bistable 256 and signal SU₁ are applied to ANDgate 258, generating an output signal which again sets bistable 248.Thus, as long as pulses SU₁ are applied, if frequency of these pulses isless than 1/60 Hz, output signal UL is continuously generated. The timermust, however be initially activated by input SUT. Timer 216 isespecially advantageous when data is input by a push button type switch.If the level of the terminal SU₁ is alternately changed between "L" and"H" levels, after the input terminal SUT has been changed to a highlevel "H" and then to a low level "L", setting in of data to thetimepiece may be readily performed simply by combined modes of operationof push buttons.

FIG. 17 shows an example of a perspective view of an electronictimepiece embodying the present invention. FIG. 18 shows a switchingmechanism which may be utilized in the electronic timepiece shown inFIG. 17. FIG. 19 is a diagram showing the operating modes of the crownshown in FIG. 17.

As shown in FIG. 17, the crown 262 is arranged to be movable in twostages in a rearward direction and in one stage in a forward direction.The crown 262 is also rotatable in either direction at each stage. Theelectronic timepiece also has a display symbol setting switch 264 and amanual shift switch 266 for setting multialarm times. The switch 266 mayalso be used for lighting a lamp. Indicated as 268 is a display face onwhich the time data is displayed. The hours and minutes, for example,12:38, are displayed on the display face 268 together with the AM/PMsymbol. This occurs when none of the switches 262, 264 and 266 isdepressed. When switch 262 is depressed, the date and days of week aredisplayed. The display is not changed if switches 264 and 266 aredepressed either separately or together and the current time stored inthe timepiece is not affected. If, however, the switch 264 is depressed,while the crown 262 is either depressed to its forward position or setto its 1st rearward position, the seconds data is set to zero.

In FIG. 18, if the crown 262 assumes either the forward position or the2nd rearward position, the input terminal SD for setting the date dayand month is grounded and thereby goes to "H" level, since lever 268operated by shaft 269 connected to the crown 262 engages contact 270. Ifthe crown 262 assumes either the 1st or 2nd rearward position, lever 271engages contact 272, which is consequently grounded. In this situation,input terminals SK and SUT for the keeping time information are groundedand go to "H" level. If the crown 262 is rotated clockewise, a sectorgear 274 is also rotated clockwise through a predetermined angle bymeans of a gear 276. Thereafter, the sector gear 274 rotates freely andpushes a spring 278 against a contact 280, causing the input terminal SMto go to "H" level. If, on the other hand, crown 262 is rotatedcounter-clockwise, sector gear 274 is rotated counter-clockwise so thatspring 278 engages with contact 282 causing terminal SH to go to "H"level. The gear 276 turns about a fixed axis, rotated by shaft 269. Acam 284 is secured to the gear 276. A lever 286 is normally pushedagainst cam 284. If cam 284 is rotated more than 180° , lever 286 ismoved toward and away from contact 288 so that input terminal SU₁ isgrounded and goes to "H" level intermittently. Since lever 286 is pushedagainst the cam 284 by its spring force, it is maintained in a stableposition spaced from the axis of the cam 284 by a minumum distance whenthe crown 262 in its normal position. The spring 278 directly coupled tosector gear 274 does not engage either of the contacts 280 and 282 whenthe crown 262 is in its normal position, but if the crown is rotatedeven only slightly, spring 278 engages either one of the contacts 280and 282. Even when the crown 262 is rotated beyond a large enough anglefor the sector gear 274 to disengage from gear 276, spring 278 is stillheld against one of the contacts. One end of a lever 290 is linked toshaft 269 and pushes shaft 269 in an axial direction. The lever 290 isprovided at its upper end with notches 292 adapted to engage astationary pin 294. If the finger of the wearer is released from thecrown 262 when it is held in the forward position, it is returned to itsnormal position by the action of the lever 290. When the crown 262 ispulled rearward from the normal position, it remains in that extendedposition. When lever of switch 264 is depressed, it engages a contact298 so that the input terminal SU₂ goes to the high level. Likewise, theinput terminal MSIN goes to the high level when lever 300 is caused toengage iwth contact 302.

FIG. 19 shows an example of operating modes of the crown and switchesshown in FIG. 18. As already stated hereinabove, if the crown 262 ispushed to the forward position a date is displayed. If, in contrast,crown 262 is pulled to its 1st rearward position, the input terminal SKgoes to the high level, and the input terminal SD remains at a low level"L". Since the input unlock signal terminal SUT is connected to contact272, it is possible to set the current time while the crown is pulledinto its 1st rearward position.

If the crown 262 is rotated counter-clockwise, i.e., upward as viewed inFIG. 19, the display of the hours data begins flashing. As the crown isfurther rotated, the hours data is incremented i.e. now data is set in.If, on the contrary, the crown 262 is rotated clockwise, i.e., downwardas viewed in FIG. 19, the display of the minutes data begins to flash.As the crown 262 is further rotated in the same direction, new minutesdata is set in. Since the data being set is caused to flash on thedisplay face before the data is incremented, there is no danger oferroneous setting. When the switch 264 is depressed without rotating thecrown 262 while switch 264 is depressed, zero setting of the secondsdigit is performed. If a seconds count of between 0-29 is displayed whenzero setting of the seconds is performed, the seconds data is set tozero. If a second count of between 30-59 is displayed during zerosetting, the seconds data is set to zero, and a carry signal isgenerated which increments the minutes data by one. There are two modesof setting the seconds data to zero, the first being to depress thecrown 262 and switch 264 at the same time and the second mode being todepress the switch 264 while crown 262 is set in its first rearwardposition. Accordingly, it is possible to perform this setting operationaccording to the needs wearer's preferences. After completion of thetime setting, if the crown is fully depressed to the forward position,whereby the date is displayed, and simultaneously an electric locksignal is applied so that accidental touching of the switches does notaffect the stored time data. If the wearer fails to fully depressed thecrown after completion of the time setting, a timer operates toautomatically apply the electric lock after a predetermined interval,for example, two minutes as shown in FIG. 16.

If the crown is pulled to its 2nd rearward position and rotatedcounter-clockwise, the setting of the month data is possible whereaswhen the crown is rotated clockwise, the setting of the date data ispossible. In this condition, if switch 264 is depressed without rotatingcrown 262, the days of week can be set. If the crown 262 is pulled toits 2nd rearward position, in which the setting of the month digit andthe date digit is possible, the display elements for the days of theweek are caused to flash. If, in this condition, crown 262 is rotated,the flashing of the display elements of the days of week is stopped, andthe display elements of the data being set begin to flash, dependingupon the direction of rotation of the crown. A clear indication is thusgiven of which data is being set.

When the crown 262 is pulled to its 1st rearward position, the settingsystem for the current time data is unlocked. When the crown is thenreturned moderately to its normal position, input terminal SUT goes tothe "L" level, thus maintaining the unlocked condition. Accordingly, thealarm time data is displayed, and it is possible to set in a new alarmtime. Under these conditions, if crown 262 is rotated counterclockwise,the hours digit of the alarm time can be set, whereas clockwise rotationof the crown permit the setting of the minutes digit of the alarm time,and if the switch 264 is depressed without rotating the crown, it ispossible to set the alarm time to either a daily or temporary mode. Whena multi-alarm facility option system is incorporated, switch 266 is usedto display the stored alarm times by stepping from one to another eachtime it is depressed. Thus it is possible to check what alarm times, ifany, are set. Each time the switch 266 is depressed, a different storedalarm time is read out and displayed. If the crown 262 is rotated,setting of the particular alarm time data being displayed becomespossible. If the switch 266 is kept depressed for a time interval ofmore than 1.5 seconds, then the stored alarm times start to beautomatically sequentially read out at a rate of one per second. Thisalarm data sweeping operation ceases when the switch 266 is released. Inaddition, the design is such that, when the wearer wishes to set in anew alarm time and a multi-alarm facility is incorporated, an automaticsearch is performed to find a data location storing an alarm time ofzero, i.e. a vacant location. This search operation takes place when theswitches are set to display alarm time data from normal mode display. Ifsuch a vacant location is found, then a display of zero hour willappear, but if all locations contain alarm time data then the last alarmtime set in will be displayed. The automatic search takes a time of 0.5seconds maximum.

In the timepiece system of this invention, the display face is switchedbetween three different data displayes, that is current time, alarm timeand date. A further display state is of alarm time zero. This is shownas a zero digit followed by a colon mark, with a blank space in place ofminutes digits. The decoder for the display driver circuit isconstructed to identify states of a word f 4 bit, and to erase or modifythe display mode by modulating the data to be displayed depending uponthe content of the data itself. These functions can be accomplished bythe data modulating unit shown in FIGS. 20A and 20B.

At first the display system itself will be discussed. There are manymethods of displaying the time data on a timepiece. Time display is justas important as timekeeping. Since there are many types of display, itis necessary to have a choice of display drive circuit to suit the typeof display.

According to this invention, the data to be displayed is selected, thentransmitted to the display unit. In addition, the display data ischopped into data bursts, before transmission.

More particularly, as shown in FIGS. 20A and 20B, the data to bedisplayed is selected from signal DATA 60, is modulated in matrix gate356, then sent out in periodic bursts at DATA.sup.Δ OUT by a choppingcircuit 352. The data modulator 350 is shown as comprising an OR/ANDgate circuit 354 and a matrix gate circuit 356. Both circuits may ofcourse be constructed using ordinary gate elements, or combined into asingle matrix gate. However use of the matrix circuit shown isadvantageous, because it is easy to understand the configuration, andbecause an inexpensive and compact ROM type matrix can be obtained whenC/MOS integrated circuits are used. It is also possible to incorporatethe various gate circuits designated as 356, 358, 360 and 362 into thematrix circuit.

A one bit delay bistable 364 is used to form a signal U*, causingflashing of the both of "units" and "tens" digit data being set in. Thisis done by increasing the pulse width of a data update indication signalU by the circuit shown in FIG. 20B. The gate circuit 362 is controlledby switches SK, SD, UL and SU₂, to select the data to be displayed. Wordpulses D₁₃, D₁₀ and D₅ select the alarm time, date and current time,respectively, and the circuit is designed to switch the data to bedisplayed in accordance with the timing of the display selection pulseD_(D). The display selection signal is passed through delay bistable 366to be delayed by one word time and to shape the signal waveform.

Gate circuit 370 generates a 16 Hz chopping signal from input CONTA,sent from the control unit 30. This serves to chop the flow of data fromshift register 388 into periodic bursts, by AND gate 389. This choppeddata is sent to the display driver 16 times per second, where it isdecoded and displayed. If terminal CONT is set to a low logic level(this is set at the time of manufacture, normally, but can also be underlogic control if required), then the data is sent in bursts asdescribed, but if CONT is set to the high logic level, data and clockpulses are transmitted continuously. Gate circuits 372, 374 and 376produce bursts of timing and clock pulses T₈,φ₁, and φ₂, which aretransmitted in synchronism with the data bursts to the display drivercircuits, and to the option unit. The latch circuit 380 ensures correcttiming for chopping φ₂ pulses. The technique of transmitting data inbursts results in a considerable reduction in power required for thedriver and option system circuits.

The following Table III is a truth table for the display driver unit,illustrated in FIGS. 22A, 22B and 22C. This table shows the relationshipbetween the sixteen possible combinations of data of 4 bit weights andthe corresponding segment display outputs, for both the display digits(showing for example hours and minutes) and the linear type display usedin the particular example of the present invention described herein todisplay days of the week and "tens" of seconds data.

                                      TABLE III                                   __________________________________________________________________________       Input data  Display driver outputs                                                                        Display driver outputs                            bit weights (digit display) (linear display)                               No.                                                                              "1"                                                                              "2"                                                                              "4"                                                                              "8"                                                                              a'                                                                              b'                                                                              c'                                                                              d'                                                                              e'                                                                              f'                                                                              g'                                                                              h'                                                                              So'                                                                              S1'                                                                             S2'                                                                             S3'                                                                             S4'                                                                             S5'                                                                             S6'                               __________________________________________________________________________    0  0  0  0  0  1 1 1 1 1 1 0 0 1  0 0 0 0 0 0                                 1  1  0  0  0  0 1 1 0 0 0 0 0 0  1 0 0 0 0  0                                2  0  1  0  0  1 1 0 1 1 0 1 0 0  0 1 0 0 0  0                                3  1  1  0  0  1 1 1 1 0 0 1 0 0  0 0 1 0 0  0                                4  0  0  1  0  0 1 1 0 0 1 1 0 0  0 0 0 1 0  0                                5  1  0  1  0  1 0 1 1 0 1 1 0 0  0 0 0 0 1  0                                6  0  1  1  0  1 0 1 1 1 1 1 0 0  0 0 0 0 0  1                                7  1  1  1  0  1 1 1 0 0 0 0 0 1  0 0 0 0 0  0                                8  0  0  0  1  1 1 1 1 1 1 1 0 0  1 1 1 1 1  0                                9  1  0  0  1  1 1 1 1 0 1 1 0 1  0 1 1 1 1  0                                10 0  1  0  1  1 1 1 1 1 1 0 1 1  1 0 1 1 1  0                                11 1  1  0  1  0 1 1 0 0 0 0 1 1  1 1 0 1 1  0                                12 0  0  1  1  1 1 0 1 1 0 1 1 1  1 1 1 0 1  0                                13 1  0  1  1  0 0 0 0 1 1 0 0 1  1 1 1 1 0  0                                14 0  1  1  1  0 0 0 0 0 0 0 0 1  1 1 1 1 1  0                                15 1  1  1  1  0 0 0 0 0 0 0 0 0  0 0 0 0 0  0                                __________________________________________________________________________

NOTE:

For the display segment outputs, "1" indicates the corresponding segmentis made visible. "0" indicates the corresponding segment is blanked out.For the serial-parallel converter outputs, "1" indicates a high leveloutput, "0" a low level. For the display outputs, "1" indicates thecorresponding display segment is made visible, "0" indicates it isblanked out.

The term "data modulation" used herein is a general term for varoustechniques whereby the nature of the data being displayed (and of thealarm time data being stored) is indicated on the display face of thetimepiece. These techniques include:

(1) Inversion of a liner type of display (see FIG. 23). This means that,for example, whereas for the display of "tens" of seconds the segmentindicating the current count is made to flash on and off, while allother segments of the seconds display are held in the on-state, in thecase of these same display segments being used to display the days ofweek data the relevant segment is also made to flash but all othersegments are held in the off-state. Thus there is a definite distinctionbetween the display of seconds data and days of the week data, althoughthe same display elements are used.

(2) Under certain conditions, a part of the displayed data may be madeto flash on and off at a periodic rate. For example, while, say, thehours and minutes data of current time is being set, i.e. updated by thewearer, the hours and minutes data on the display face flashes. Thus thewearer can be certain that he is not accidentally altering some otherdata in the timepiece.

(3) The nature of the data being displayed, in the case of digital data,may be indicated by, for example, a symbol adjacent to the displayeddata. In the embodiment described herein, a stroke is displayed betweenthe months and days of month digits, whereas a colon is displayedbetween the hours and minutes digits. Thus discrimination may be madebetween the two types of data although the same display elements areused to display them.

(4) A mark or symbol may be used to indicate some continuous internalcondition of the timepiece. For example in the embodiment describedhere, one kind of alarm symbol is kept on continuously so long as analarm time is stored in the timepiece, and another symbol is kept on ifthe alarm time is of the "daily" type.

(5) The displayed data may be modified by an additional symbol, forexample the display of hours and minutes is modified by the AM/PMsymbol.

(6) Although not shown in the present embodiment, where a liquid crystaldisplay is used additional data may be read out by an additional displaylayer situated behind the layer of liquid crystal display elements.Information marked on each element of this "background" layer will berevealed when the display element situated above it is switched fromopaque to transparent. Thus, for example, when the display elementcorresponding to weekday Tuesday is switched on, the information "TUES"could be revealed.

The display of data is controlled by:

(1) Switching operations (switching on and off of the data on thedisplay face)

(2) The content of the data to be displayed (for example, erasure of theminutes data when alarm time zero is displayed)

(3) Externally input data (for example, control by inputs such as DINfrom the option unit)

Although in this specification the data modulating unit is connected toa serial shift register, it should be understood that the invention isalso applicable to data storage systems other than a serial shiftregister, for example, a parallel system utilizing static type bistablecircuits such as shown in FIG. 13.

Turning back to FIGS. 20A and 20B, the information printed at the rightof the matrix gate 356 describes the selection functions of thecrosspoints on the rows of the matrix. The DATA 60 output from the shiftregister ring is delayed 4-bit more than output from stage Q₁ of theshift register ring. The timing of data output from Q₁ is used as thereference timing for the timepiece data. The suffixes of the word pulsesignals applied to the matrix 356 are therefore larger by one than thesuffixes applied to the corresponding word pulses utilized for carrydetecter 72, so as to match data 60 and Q₁ data. The output from thegate circuit 354 is combined with the output of matrix gate 356 so as tomodulate the data displayed. A signal φ1 Hz is formed by a latchcircuit, shown in FIG. 20A, and converted by gate circuits 352 into twosignals φ_(1F) and φ_(1G). F actuates display flashing of the entiredisplay when alarm coincidence occurs, and G represents a flashinginhibiting signal sent from the control unit in FIG. 8A. The word pulsesD₁₄ and D₁₅ are OR'd and applied to matrix gate 356 so as to erasedisplay of the minutes data of alarm time data if the alarm time hoursdata has been set to zero. This permits a clear indication that no alarmtime has been set in.

Timing pulse D₉ T₁ is applied to the matrix to suppress the AM/PM symbolwhen date data is displayed. (The AM/PM data bits is output from Q₁ ofshift register 58 at time D₈ T₁.)

The function of the input D₅ T₈, designated "SECONDS" inverted displayis as follows. Looking at Chart III, it can be seen that adding a bit ofweight 8 to the output counts 0 to 7 of the serial-parallel converterwill result in the display sequence shown in the lower half of the"linear display" outputs. This is a display sequence where the segmentcorresponding to the data count is held "OFF", and the other segments(apart from that connected to S₆) are held "ON". As explainedpreviously, this is the opposite display mode to the days of week data,which corresponds to the top half of the right hand portion of TableIII. Thus a distinction is made between the days of week data displayand the seconds data display, although the same display elements areused.

The "tens" display digit of the date days is suppressed by word pulseD₁₂ applied to matrix gate 356, whenever this "tens" digit is a zero.The suppression of this digit when it is zero is normally considereddesirable in a wristwatch.

For the timepiece display of this invention, it is advantageous todisplay the months data only when it is specifically required. This isbecause, since the same display elements are used for months data andhours data display, greater clarity is given to the date display if themonths digits are suppressed. Thus, normally when the wearer operatesthe external switches to obtain a date display, only the day of themonth (in place of the minutes digits) and the day of the week (on thelinear display, in place of "tens of seconds") will appear. However, ifthe wearer operates the switches to the "date setting" mode, then themonth number will also appear on the date display. This is achieved bythe input "DATE DISPLAY WITH MONTH SUPPRESSED", using word pulse D₁₃, tomatrix gate 356. Referring to Table III, it will be seen that an outputof "all ones", i.e. "15" state of the word, from the serial-parallelconverter will result in a display of "all zeroes". Thus by applyingword pulse D₁₃ while the months data is entering shift register 388, themonths data is converted to "all ones", and thereby is blanked out onthe display face.

The input D₁₀ to matrix gate 356, gated by flashing signal φ1G normallycauses flashing of the weekdays display when the date data is displayed.This occurs when signal G is in the "L" state, which occurs when theinput switch signals are in the condition (SH·SM+SH·SM=L). Thus, whensignal G is "H", this flashing is suppressed.

The input D₅ ·T₁ causes flashing of the "tens" of seconds data. Thelogic product D₅ ·T₁ is equivalent to D₅ ·(T₂ +T₄ +T₈). Referring toChart III, it will be seen that causing the serial-parallel converteroutputs, "2", "4" and "8" to go to the "all ones" state causes thedisplay outputs S0 to S5 to become "all ones". Thus, the "0" displayoutput which is indicating the current "tens" of seconds count isswitched to "1" when input D₅ T₁ is at "H" level. Since D₅ T₁ is gatedinto matrix gate 356 at a frequency of 1 Hz by signal φ1G, the segmentof the seconds display which is indicating the current time count willbe flashed on and off at a 1 Hz rate.

In the timepiece system illustrated, only the six successive states ofthe "tens" of seconds data are output from the display driver circuit,so that 0, 10, 20, 30, 40, 50 and 60 second times are sequentiallydisplayed. It is however possible to arrange the system such that"units" of seconds are also displayed, and input D₄ (1-second F_(L)) tomatrix gate 356 caused the "units" of seconds data also to flash whendisplayed.

As previously explained, when the wearer sets new data into thetimepiece for current time, alarm time or date, the corresponding partof the display is caused to flash at a periodic rate. This is caused byinputs φ₁ Hz and U* to matrix gate 356. It is necessary that U* have aduration of two word times. This is because, for example, while theminutes data is being set, both the "tens" of minutes and "units" ofminutes display digits should flash simultaneously. This is accomplishedby extending the action of input U, from Control Unit 30, to two wordpulse durations, by means of gates 358 and 356, together with latch 364.Thus the displays of "units" and "tens" of current time minutes, alarmtime minutes and days of the month are caused to flash together whentheir particular data is being set by the wearer.

To flash the daily alarm symbol, date symbol and AM/PM symbol, thesignals generating these symbols are modulated by signals φ_(IF),φ_(IF)or φ_(1G).

Continous enable terminal 384 is normally set to the level "L" by anoutput from bistable circuit 389, which is repeatedly reset by a narrowpulse signal BD₃ T₈ at a frequency of 1 Hz. The CONTA signal output isobtained by detecting the instant when the 1/16 second data in thetimekeeping register becomes "0". This output is utilized by the latchcircuit 386 to form an output enable signal having a width of 1 memorycycle, or about 4 milliseconds which is delayed by about 1/2-bit timewith respect to the instant when the 1/16 second data becomes "0". Thisenable signal is latched into 386 at timing T₈ φ₁ and is used togenerate periodically chopped bursts of data and clock signals whichcontain no spurious transient pulses.

To this end, it is passed through OR gate 370, so that if so desired, acontinuous enable signal may be obtained by setting the CONT terminal tothe "H" level. (This present of the CONT terminal would be performed atthe time of manufacture). The enable signal is then applied to AND gate376, to generate bursts of φ₂ clock pulses. It is then delayed in latchcircuit 380 so that bursts of φ₁ clock pulses are gated out of AND gate374, beginning one period of φ₂ after the φ₂ clock bursts (see timingdiagram FIG. 8) and continuing for exactly one memory cycle. Thisdelayed output enable signal also gates out concurrent bursts of data(designated D.sup.Δ) and of timing pulses T₈.

The facility for sending data out in synchronized bursts has theadvantage of greatly reducing power requirements for the subsystems towhich the data is transmitted. It permits subsystems such as the displaydecoder and driver circuits, and the option system, to be updatedperiodically at a low frequency, while the basic timekeeping systemoperates continuously at a high frequency. Thus, energy dissipated incharging and discharging stray capacity in terminals and leadsconnecting the various integrated circuit chips of the system is greatlyreduced. The burst signals are designated DATA.sup.Δ OUT, T₈.sup.Δ,φ₁.sup.Δ and φ₂.sup.Δ, and have a burst repetition rate of 16 Hz andburst duration of one memory cycle of shift register 58 in thetimekeeping system. FIG. 21 shows one possible circuit configuration forthe alarm unit 34. The input designated DATA 60 comes from the input tothe 60th bistable circuit in the time data storage shift register ring,in accordance with the previously described numbering system. Similarly,the data input to the 28th bistable circuit of this shift register ring,i.e. the output of the 29th bistable circuit, is designated DATA 28.Coincidence between the logic levels of DATA 60 and DATA 28 is detectedby Exclusive-OR gate 404, causing its output to go to "L" logic level.In this way, the alarm time tAT is compared with real time tKT. The DATA60 output signal is delayed by the duration of one word time relative tothe timing reference serial adder outputs designated as Q65. Since theDATA 28 signal is delayed by 8 word times relative to DATA 60, thenduring times D₆, D₇, D₈ and D₉ the DATA 60 signal represents theminutes, tens of minutes hours and AM/PM state for the current timerespectively while the DATA 28 signal represents the minutes, tens ofminutes, hours and AM/PM state (or other symbol) of the stored alarmtime respectively.

The detection of timing coincidence is initiated by setting the outputof bistable circuit 400 (which has an override reset input) to "H" levelat time D₅ T₈ φ₁. Any subsequent lack of coincidence between DATA 60 andDATA 28 inputs cause bistable circuit 400 to be reset, by the output ofExclusive-OR gate 404. If complete coincidence does occur i.e. tKT=tAT,bistable circuit 400 remains in the set condition for the duration ofdigit pulses D₆ to D₉. More precisely, the comparison between the realtime data tKT and the alarm time data tAT is continued until time D₉ T₈φ₁, when the output state of bistable circuit 400 is transferred toD-type bistable 402 through a one bit delay bistable 401. It should benoted that there is a time delay between detection of coincidence forreal time tKT and alarm time tAT in gate 404 and the writing in of thiscondition to bistable circuit 402. Because of this, signals DATA 60 andDATA 28 are actually compared during the time interval between D₆ T₁ φ₁and D₉ T₄ φ₁.

If only a single alarm time facility is incorporated, then the alarmtime data from DATA 28 is always at the "L" level at times D₉ T₂ and D₉T₄. However if alarm time data is transmitted from the option unit, itis possible that the alarm time data will be "H" level at either ofthese times.

Coincidence between alarm time and real time is indicated by the outputof the bistable 402 going to the "H" logic level. It can be seen that,since complete coincidence between tKT and tAT will only be apparentwhile the value of the "minutes" data is the same for both of them, theoutput of bistable circuit 402 will only remain in the "H" logic statefor one minute when complete coincidence is detected, and will be in the"L" state at all other times.

Bistable 406 (edge-triggered type), is set by the "L" to "H" transitionof the output of bistable 402. Its output is used to control an audiblealarm signal. According to this invention, the alarm consists of burstsof 2045 Hz tone with a duty cycle of 25%, a repetition rate of 1 Hz. Ifthis signal is further modulated at a frequency of several Hz, theresultant audio alarm somewhat resembles the chirping of a cricket. Thisis not irritating, but attracts the attention of the user.

Edge-triggered bistable circuit 408 is set by the rising edge of theoutput from bistable 406, and its output serves to actuate flashing ofthe timepiece display. Both bistable circuits 406 and 408 have overridereset inputs, and can be reset by either of the gate inputs S₁ and S₂,or by the STOP data input of the timepiece. The user can therefore inputa signal to the timepiece circuitry to confirm that he has noticed thealarm signal, and the timepiece will then respond to his signal bystopping the alarm indications. Even if such an alarm confirmationsignal is not sent, the circuit is designed to automatically terminatethe audible alarm signal after one minute. This is so as to minimizepower drain on the battery, and avoid generating unwanted noise. In thisevent, however, flashing of the timepiece display will continue untilthe user inputs an alarm confirmation signal. Bistable 406 is connectedsuch that it is reset by the output of gate 410 one minute after alarmcoincidence is first detected.

Since the audible alarm consists of tone bursts at a frequency of 2048Hz with a duty cycle of 25% and a repetition rate of 1 Hz, it containsfrequency components within the range of about 2 KHz, the range to whichthe human ear is most sensitive. Also, because of 25% duty cycle of the1 Hz repetition rate, the power required to actuate the audible alarm isgreatly reduced, thereby prolonging battery life.

The control signal for the audible alarm is applied to the base of anNPN type transistor, connected in common emitter configuration, whichhas a 100 Kohm resistor in series with its emitter lead. The activatingcoil for a piezo-electric buzzer is connected in series with thecollector lead of the transistor. It is also possible to use anelectro-dynamic type buzzer in place of the piezo-electric type. Ineither case, the increase in battery current required to operate thebuzzer is only about 10%.

The output from bistable 402 is delayed by bistable 412. Gate circuit410 serves to detect non-coincidence between the logic levels of theoutputs of bistable 402 and 412. It therefore generates an output on thefalling edge of the output of bistable 402, at the end of the one-minuteduration coincidence signal (when tKT=tAT). DATA 28 and word pulse D₉are applied to AND gate 413 to detect whether a daily alarm conditionhas been set. If it has, bistable 414 is set at time D₉ T₈ φ₁. If atemporary alarm has been set in, 414 output Q remians at "H" leve. Thisoutput is designated QER. An erasure signal ERASE is thereby generatedby a logical combination of the alarm coincidence signal ALDET frombistable 406, a logical negation QER of the erasure inhibit signal, theinversion of the unlock signal, UL, a word timing signal and signal ATO.The latter indicates that the stored alarm time is set to zero.generation of the ERASE signal causes the corresponding alarm time datato be set to zero.

The logic relationship of the above is:

    ERASE=(D.sub.14 +D.sub.15 +D.sub.16 +D.sub.1 T.sub.8)·UL·(ATO+QER·ALDET)

Even if the alarm time being set in should coincide with real time,erasure will not occur while the alarm setting is taking place. Erasurecan only occur under the normal operating condition, when UL is in the"H" logic state. If the state of UL were not made one of the controllinginputs to the ERASE generating circuit, setting of the temporary alarmwould be extremely difficult. This is because, if the alarm time beingset in should happen to coincide with current real time, while settingwas taking place, the alarm time data would be erased.

Usually, symbols giving information concerning the alarm data can onlybe displayed together with the digits of the displayed alarm data.According to this invention, however, particular alarm symbols such asthe daily alarm symbol and set symbol can be made to appear with thecurrent time display. This enables the user to easily check the state ofthe alarm setting at any time. The condition of zero alarm time beingset in is detected and stored in latch circuit 204 in FIG. 11B, theresultant output being designated ATO. As well as being applied to thealarm unit, as described above, this signal is input to the datamodulating unit 36 (FIG. 20B). Here, it is used to inhibit the output ofalarm time minutes data to the display driver unit, thereby causingblanking of alarm time minutes digits when the alarm time zero conditionis set in.

To drive liquid crystal display elements, the level shifter circuits 40are used. Details of the level shifter circuitry are shown in FIGS. 24Aand 24B. After the "L" logic level voltage of the data has been changedby level shifter 40, it is sent to a bit serial-parallel converter 42,made up of shift register stages 502, 504 and 506. Outputs fromconverter 42, P₁, P₂, P₄ and P₅ are applied to decoders 508 and 510,whose outputs are written into storage latches in word serial-parallelconverter 46. Decoder 508 provides outputs for display digits, whereasdecoder 510 provides outputs for a 7-segment linear display. A transferswitching circuit 512 is used to select the outputs of decoders 510 and508 so that linear display outputs S₀ through S₆ can also be used todrive display digits, if this is desired. As stated previously, thetruth table for the decoders is shown in Table III. Word serial-parallelconverter 46 is made up of a number of latch circuits 514 through 526,514 through 524 being used to convert decoded serial data words from thedecoder outputs into static outputs, i.e., parallel form. These latchcircuits provide fixed output signals as long as the data does notchange. The latch circuit 526 functions to slightly delay the φLC inputsignal.

As shown in FIG. 24D the display driver 20 comprises an equal number ofAND-NOR gate circuits and latch circuits. Each latch circuit producessignal φCOM when its Q output is at the low level, and a signal slightlylagging the signal φCOM in phase when the Q output is at the high level.In FIG. 24D each display element is connected between output φCOM andthe output φdj of the corresponding driving circuit. A voltage of zerois applied to the element when the latch output is at a low level, and avoltage having a frequency equal to that of the output φCOM when thelatch output is at a high level.

Timing pulse reproducing circuit 530 comprises shift register stages532, 534, 536 and 538 for reproducing timing pulses D₁ T₈ φ₁, D₂ T₈ φ₁,D₃ T₈ φ₁, D₄ T₈ φ₁ and D₅ T₈ φ₁ and gate circuits 540. The timing pulseD₅ *T₈ φ₁ is applied to latch circuits 514 and 516 to act as a clocksignal. Similarly, timing pulses D₄ *T₈ φ₁, D₃ *T₈ φ₁, D₂ *T₈ φ₁ and D₁*T₈ φ₁ are applied to latch circuits 518, 520, 522 and 524 respectively.

The signal from output terminal M_(DD) is used to actuate display ofcertain of the markings and symbols shown in FIG. 23, for example symbol572. This indicates a time display. The signal from output terminalM_(DY/d2) actuates display of a symbol showing that a daily alarm timehas been set, for example the symbol 562 shown in FIG. 23. Output M_(AL)actuates display of a symbol which indicates alarm time has been set,for example symbol 564 in FIG. 23. The appropriate daily alarm symbol ortemporary alarm symbol will be displayed even while an alarm time isbeing set, with the alarm time being displayed, as well as when thetimepiece is displaying current time in the normal operating condition.The output from terminal M_(DD) actuates display of symbols such as 566,indicating that a date is being displayed, and 568, indicating thecurrnet weekday. The output M_(PM) actuates display of a segment 570,which when combined with segment 562 activated by output M_(DD) providesdiscrimination between the displays of PM and AM. 574 represents a"seconds" frame, which is also activated by output M_(DD). OutputM_(DY/d2) is switched so as to display segment 578 (d₂), shown in FIG.23, when a 7 segment display is designated. It should be note that, ifthe display has to show solely time data, then the display digit shownas the second from the right on FIG. 23 only has to handle counts offrom one to six (i.e. the "tens" digit of minutes or days.) Accordingly,segments d₂ and q₂ are either on or off together, and so these segmentsmay be driven by a common drive output. However, if this invention isapplied to a chronograph or calculator facility, where fractions ofseconds or the full range of decimal digits must be displayed, then d₂and q₂ must be driven by separate drive outputs. The leftmost, or firstdigit of the display shows only the symbol "1". The second digit, 580,is displayed by segments a₁ through g₁, the third digit 582 by segmentsa₂ through g₂ and the fourth digit 584 by segments a₃ through g₃. The7-segment linear type display of "tens" of seconds 586 is provided bysegments S₀ through S₆. These can alternatively, drive a 7-segment digitdisplay if input S_(DE) is set to "H" level.

As has been described hereinabove, the potential of the signals appliedto the inputs of the display driver unit are switched between V_(DD) (0volts) and V_(SS1) (-1.5 volts) but according to this invention levelshifter circuits 40 are connected at the imput of the driver unit, tochange the "L" logic level of these signals from V_(SS1) to V_(ss2) (-3volts). An example of the level shifter circuit is shown in FIG. 24A.The configuration is of an inverter stage, to which logic input SS1 isapplied, and whose input and output are connected to opposite inputs ofa bistable. This bistable, constituted by CMOS transistors 601 to 609,is based on two NAND gates. Each of these gates has one input connectedto the output of the opposing gate, the other input being driven fromthe complementary input. The MOS FET transistors 602 and 604 areproduced such that in the circuit arrangement shown they are not driveninto the "pinch-off" condition by the potentials applied to their gates.Thus, as the input logic level is switched from " H" level V_(DD) to "L"level V_(SS1), the output logic level is switched from between V_(DD)and V_(SS2), due to the conducting paths through trasistor pair 601 and607, and transistor 606, being opened or cut off by the switching of thebistable.

A modified form of this level shifter design is shown in FIG. 24B. Itshould be noted that it would be possible to reduce the powerconsumption of the display driver unit shown in FIGS. 24A and 24B byperforming the level shifting at the display drive outputs, since thenumber of logic level transitions performed by these circuits per secondis much less than at the inputs. In this case, latch circuits 514 to 524could be replaced by the level shifter circuits shown, modified so thatthe bistable has SET and RESET inputs. However, this results in anincrease in the total number of FETs required in the display driverunit.

An example of the display driver circuit is shown in FIG. 24D. As isnormally done in liquid crystal display driving, the display segmentwhich is to be made visible has a periodic squarewave alternatingvoltage applied to its electrodes. It is a feature of the presentdesign, however, that a delay time is arranged at the stage of eachelectrode applied voltage transition when the applied voltage is zero.During this delay time, the electrical charge on the electrodes isdischarged through by passing CMOS FETs connected to the electrodes, sothat this discharge current is not passed through the supply battery ofthe timepiece. This results in a reduction in the power required todrive the display of about 50%, as compared with conventionaltechniques. This delay is accomplished by timing signal D₁, applied tolatch circuit 761, which produced delayed drive signal φ_(LC*). To blankout a display segment signal SJ is set high. Alternating voltages ofidentical phase and polarity are thus applied (i.e. φ_(LC)) through NORgate 762 and inverter 763, to the corresponding segment electrodes 764and 765.

Referring now to the display drive unit shown in FIGS. 22A, 22B and 22C,the level shifter circuits 40 are indicated by a set of square blocks atthe inputs on FIG. 22A. After level-shifting, the data input isconverted from parallel to serial form by bit serial-parallel converter42, composed of shift register circuits 502, 504 and 506. The fourparallel outputs from the converter 42 are applied to decoders 508 and510, which generate display segment data outputs for digital and analog(linear) display formats respectively. For some applications, an analogtype display will not be incorporated, all readouts being in digitalform. In order that a standardized IC chip may be utilized for bothtypes of application a "transfer" circuit 512, controlled by inputS_(DE) is included. When input S_(DE) is "H", then the outputs ofdecoder 508 will appear at the transfer circuit outputs. This would beapreset at the time of manufacture of the timepiece. In the casedescribed here, input S_(DE) would be set permanently to the "L" logicstate. The outputs of the decoders 508 and 510 corresponding to theweights of the input bits are shown on Table III. Decoder 508 generates8-segment outputs, for the digital part of the display, and 510generates 7 outputs for the analog part.

The composition of each element of the decoder is shown in FIG. 24C. Anassemblage of MOS FET transistors constitutes a matrix of AND/OR gates,whose output is latched into bistable circuit 760. This techniqueenables easier manufacture of the decoder in highly compact form. Theincoming data which is to be displayed is sequentially stored in wordserial-parallel converter 46 by clock pulses D₁ T₈ φ₁ to D₅ T₈ φ₁. Theseare generated by an input shift register consisting of stages 532 to538, and are initiated by input D_(D) from the data modulation unit. Itshould be noted that since the timing of D_(D) is determined by theoutput of data selector 362 in the data modulation unit (FIG. 20B), thissignal effectively selects which of the three data categories, currenttime, alarm time and date, will appear on the display.

One example of the option unit 13020 for this invention is illustratedin the block diagram shown in FIG. 25. The option unit is combined witha standard unit 10 of the timepiece system. Various control signals aretransmitted between the standard unit and the option unit throughterminals 13011, 13012, 13021 and 13022 and interconnecting conductors13041 and 13042, the direction of flow of signals being designated byarrows shown on conductors 13041 and 13042. Either one of theinterconnecting conductors 13041 and 13042 may be omitted, depending onthe particular system design. Input terminal 13061 is shown, connectedonly to the option unit, but in some cases this terminal may be omitted.

Main operation unit 13031 is based on a data storage register if only amulti-alarm option facility is intended; or on an operating unit, a datastorage register, and timing pulse generator where an automaticgain/loss compensation option facility is intended; or an operating unitand a data storage register where a calculator option facility isintended; or a pressure detector, a data converter and a data storageregister where a blood pressure monitoring option facility is intended.A control unit 13032 is provided. When a multi-alarm option facility isintended, the control unit 13032 generates signals, which cause each ofa number of alarm times stored in the option unit to be successivelycompared with the current time, and, on demand by the wearer, commandsignals which cause the alarm times stored in the option unit to besuccessively read out on the timepiece display face. Where a gain/losscompensation option facility is intended, the control unit 13032produces a signal causing the commencement of an error measurement, anda command signal to cause a pulse generating circuit in the option unitto generate gain/loss correction pulses required to correct any error.In the case of a calculator option facility, the control unit 13032produces command signals causing exchange of data between the calculatorand various data storage locations in the option unit, in response tocalculate command signals such as ×, ', +, =, etc.

In addition, the control unit 13032 may also be constructed such that itstores the entire operation sequence of the option unit, or part of thesequence. It may also be constructed so that a portion of the standardunit is controlled by the option unit, through signal conductor 13041.For example, in the case of a multi-alarm option system, uponcoincidence between one of the alarm times and the current time, thisalarm time data is erased from the option unit storage registerautomatically. A gate circuit whereby data is transmitted from optionunit 1320 to the standard unit is closed when alarm coincidence isdetected, and a control signal is produced by the control unit causinginterruption of the supply of clock pulse to the shift register of theoption unit. Just previous to this time, the alarm time data coincidingwith current time has been supplied to the data storage register of thestandard unit. After one minute, the supply of clock pulses from thestandard unit to the option unit is resumed, thus sequentiallytransferring other alarm time data to the standard unit from the optionunit. When the normal current time display is changed to an alarm timesetting display, by actuating an external operating member, the controlunit produces a signal that causes the data stored in each location ofthe option data storage register to be examined sequentially. When alocation is found in which there is no alarm time stored, or after apredetermined time, for example 0.5 second, a signal that terminates thesearch is produced. If a vacant storage location is found, a signal isproduced, causing termination of the supply of clock pulses to the datastorage shift register of the option unit. If no vacant location isfound, the search is automatically terminated, after 0.5 secondsmaximum. In this case, the lastly set alarm time is transferred to thestandard unit and displayed, and the supply of clock pulses to theoption unit storage shift register is terminated. The new desired alarmtime data is now written into the data storage register of the standardunit by the wearer, using external control members. As stated above, atthe end of the termination of the search for a vacant alarm location,the data flow between the standard unit and the option unit has beeninterrupted. When the wearer now actuates another control member, acircuit path is opened allowing flow of data from the standard unit tothe option unit by the control circuit of the option unit. The new alarmdata is then transferred from the standard unit to the option unit at atiming such that it is written into the vacant data location.

If the system incorporates a calculator option facility, the techniqueof sending clock pulses in bursts may also be applied, while maintaininga high speed of computation. When a data entry is made to thecalculator, or an operating command is given to it, this causes the CONTterminal of the standard unit to be set high for a time depending on theparticular operation. This in turn causes a continuous train of clockpulses at high frequency to be sent to the calculator option unit. Whenthe computation or entry is completed, the clock pulses may be thenagain sent in periodic burst, as described for the multi-alarm optionfacility. This technique enables the power requirements for aminiaturized calculator to be reduced from several milliwatts to about 1microwatt, a reduction of the order 10³.

The use of a combination of standard unit and cotrol unit offers anumber of advantages. Since the clock pulses used in the option unit aregenerated by the standard unit, while they are controlled by a controlunit in the option unit, there is a saving of component elements and acorresponding reduction in power requirements. In addition, detectioncircuits can be incorporated in the control unit to monitor the statusof data stored in the option unit, the state of external control membersor such things as supply battery voltage. Also, the use of suchdetection circuits within the option unit makes it possible to utilizethe same external operating members for varous purposes, therebyreducing the number of such external members required, as will later beshown in the description of the option unit operation. As an example, ifboth an automatic gain/loss compensation facility and a multi-alarmfacility are incorporated, the same external switch can be used both toupdate the time data and also to cause the various stored alarm times tobe sequentially displayed. It is also possible to design control unit13032 such that it can control certain operations within the standardunit also. For example, if alarm times which include date data arestored in the option unit, the control unit can produce command signalscausing the colon of the digital display (indicating time data) to beerased and a stroke together with the letters "DATE" to be displayed.Where an automatic gain/loss adjustment facility is incorporated, again/loss compensation signal can be sent from the option unit to thetiming pulse generator within the standard unit.

Interconnecting conductor 13042 transmits data, clock pulses and varioustiming signals, as well as DC power to the option unit. If the standardunit is utilizing a clock pulse frequency of 16,348 Hz (φ₁ and φ₂), forexample, bursts of these clock pulses (φ₁ Δ and φ₂ Δ) are transmitted tothe option unit at a repetition rate of 16 Hz. Thus the means clockfrequency of the option unit is 1,024Hz. Use of the burst techniqueenables data to be transferred between the option unit and standard unitin synchronism, in spite of the difference in mean clock frequencies.This has the advantage of obviating the need for a separate clockfrequency generator in the option unit, thereby decreasing powerconsumption.

Signals φ_(UC1) and φ_(UC2) are sent to the option unit to enablevarious timing pulses within the word times D₁ to D₁₆ to be regenerated.These signals may also be used, if necessary, to provide switchingpulses for a voltage booster circuit in the option unit. This boostercircuit is only required for certain types of liquid crystal displays.The higher voltage which it supplies is applied to the circuitry of thedisplay driver unit. If necessary, other circuits of the option unit maybe operated from this boosted output voltage, or from an intermediatepoint within the booster circuit.

The combination of the standard unit with an option unit offers numerousadvantages, not afforded by either of the units used separately. This isbecause the particular features of each unit are combined to the bestadvantage.

FIG. 26 shows a basic block diagram of one example of an option unitproviding multi-alarm and gain/loss functions. For simplicity, thewiring for the word pulses, timing pulses and clock pulses, etc., is notshown. Table IV gives a breakdown of the functions of the various blocksshown in FIGS. 27A, B and C. In this table, classification group "a"comprises the blocks which generate the basic timing signals required tooperate the option unit. Classification group "b" covers those blocks inwhich various conditions of the data, for example coincidence between analarm time date and the current date, are detected. Group "c" covers theblocks which generate various control signals, which control theoperation of not only the option unit, but in some circumstances thestandard unit operation also. Group "d" comprises various data controlgating circuits, controlled by signals from the standard operating unit,option unit control signals, etc. Comparing FIG. 25 to FIG. 26, itshould be noted that FIG. 26 is a basic block diagram of the embodimentof the present invention described herein, corresponding directly to themore detailed diagrams of FIGS. 27A to C. As shown, timing and controlpulses sent from the standard timekeeping system 10 causes timing pulses13065 to be produced by primary pulse generation circuits 13069, andapplied to state detection circuits 13062, control signal generatingcircuits 13063 and main operation circuits 13064. The groupclassifications "a", "b", "c", "d" and "e" in table IV correspond toblocks 13069, 13062, 13063 and 13064 in FIG. 26, as well as to thecorresponding to blocks in FIGS. 27A to C.

                                      TABLE IV                                    __________________________________________________________________________    Classification                          Outputs                               Group           Number                                                                             Designation                                                                           Function   (in FIGS. 27A to                      __________________________________________________________________________                                            27C)                                    a: Primary pulse                                                                            1430 Qi-RP-a Reproduce composite                                                                      Q.sub.1 -Q.sub.16 and                                                         φ.sub.α+β                generation                 word timing pulses.                                              1431 Tj-RP-a Reproduce  T.sub.1 -T.sub.8, T.sub.12,                                                   T.sub.24                                                           Bit timing pulses.                                               1451 Width-a Synthesis of signals                                                                     WKT, WDT, WATI, WATO                                               determining transmit-                                                         ting and receiving                                                            data time durations                                              1454 TPG-a   Synthesis of                                                                             T.sub.8 φ.sub.1, D.sub.10                                                 T.sub.8 φ.sub.2, etc.                                          composite timing                                                              signals.                                           [b: state detection]                                                                        1410 OHAT-b  Alarm time zero                                                                          OHAT                                                               detection                                                        1411 QOHER-b Detection of                                                                             QOHER                                                              "all ones" of alarm                                                           data                                                             1424 DT-DET-b                                                                              Detection of                                                                              ##STR4##                                                          coincidence of alarm                                                          date and current date                                            1425 AT-DET-b                                                                              Detection of                                                                             DETAT, QERAT                                                       coincidence of alarm                                                          time and current time                                            1427 AT-DISP-                                                                              Alarm time display                                                                       QA, Q .sub.3 AT 2○ , Q                                                 .sub.3 AT 1○                                        DET-b   state detection                                                  1429 KT-DISP-                                                                              Current time display                                                                     QKT                                                        DET     state detection                                                  1482 DT-GATE-b                                                                             Count of days, for                                                                        ##STR5##                                                          control of automatic                                                          gain/loss circuits                                 c: control    1402 SB-C    Output control                                                                           SB.sub.○.sub.1,                                                        SB.sub.○.sub.2,                                                        SB.sub.○.sub.3                   signal                                                                        generation                                                                                  1403 SA-c    Input control                                                                            SA                                                    1420 MAN-SHIFT-c                                                                           Manual shift, to                                                                          ##STR6##                                                          enable display of                                                             the various stored                                                            alarm times                                                      1426 SRG-STOP-c                                                                            Halting operation                                                                         ##STR7##                                                          of data storage                                                               shift register                                                   1452 MAR-SET-c                                                                             Mark set   ALI.sub.○.sub.1,                                                       ALI.sub.○.sub.2,                                                       ALD.sub.○.sub.1,                                                       ALD.sub.○.sub.2                                1483 INPUT   Control of operation                                                                     P.sub.1, DGR                                               ANALYSIS-c                                                                            of automatic gain/loss                                                        adjustment                                         d: gating system                                                                            1401 OUT-CONT-d                                                                            Data output                                                                              DOUT, D.sub.CL                          around main                control gate                                       component                                                                                   1408 CLOCK-  Clock pulses                                                                             φ.sub.1 *, φ.sub.2 *                               CONT-d  control gate                                                     1409 DATA-   Data input D.sub.IN 1○ , D.sub.IN                                                 2○ , D.sub.IN 3○                             DEMOD-d demodulating gate                                                1407 DIN-GATE-d                                                                            Shift register data                                                                      1407-OUT                                                           input control gate                                               1406 AL.sub.○.sub.1-d                                                               Mark input gate.sub.1                                                                    SRG-448-IN                                            1405 AL.sub.○.sub.2-d                                                               Mark input gate.sub.2                                                                    SRG-438-IN                                            1404 DT-ER-d Date data  AXO                                                                erasing gate                                                     1490 SRG-RING-e                                                                            Data storage shift                                                                       SRG-OUT(111, 121, 311,                                             register ring                                                                            411)                                    e: main operating                                                                           1481 COMP-e  Counter and                                                                              Q.sub.31 -Q.sub.36                      system                     comparator for                                                                gain/loss                                                                     adjustment                                       __________________________________________________________________________

In describing the construction and operation of the example of theoption unit shown in FIGS. 27A, 27B and 27C, the overall functions ofthe unit will first be outlined. The option unit comprises a 64 bitshift register ring 1490 to accommodate alarm data, a group of gateblocks 1401 through 1454 including various gate circuits for controllingthe shift register ring, circuits generating various signals, the gates,an automatic gain/loss adjusting block 1480, and a "flexible" circuitblock 1470, which can be utilized are required by the particular design.The 64 bits of the shift register ring 1490 can accommodate either foursets of alarm time data comprising hours and minutes or two sets ofalarm time data comprising hours, minutes, month and date. It ispossible to increase the amount of alarm time data by adding additionalshift reigster stages. The alarm time data includes AM/PM informationand the wearer can select either a daily alarm mode, whereby an alarm isgenerated at the same time every day, or a temporary alarm mode in whichalarm coincidence is detected only once, generating an alarm warning andthereafter the corresponding alarm time data is automatically erased.The setting of multi-alarm data in the option unit is performed usingexternal operating members connected to the standard unit, so thatadditional operating members for the option unit are unnecessary. Bymeans of the gain/loss adjustment system, it is possible to compensatethe oscillation frequency of a mass produced quartz crystal to anaccuracy of 7×10⁻⁷, without using trimer capacitors or other measures.This accuracy results in an error of the order of two seconds per month,which is less than can be obtained by a quartz crystal oscillatoradjusted at the time of manufacture of the timepiece. According to thisembodiment it is possible for the wearer to quickly adjust the timepieceto a very high accuracy, by means of internal circuitry which measuresthe gain/loss of seconds over a period of one week. Since this errorwill vary according to such factors an ambient temperature (which isaffected by the wearer's daily activities), aging of the particularquartz crystal used, etc., this method is basically preferable to afactory preset frequency adjustment. The adjustment is performed by thewearer resetting the seconds data of the watch to zero (by depressing aswitch) at the "zero" time of, say, a standard radio time signal.Precisely one week later, at the same "zero" time signal, the weareragain resets the timepiece seconds display to zero. Compensation has nowbeen automatically achieved.

Gate circuits 1404, 1405 and 1406 are provided for shift register ring1490 so that data may be rapidly input to the register in semi-parallelform. These gate circuits are also used to set in alarm daily/temporarydata, and to erase stored data when necessary as will be describedlater. Output SRG-111 is sent to the standard unit from the option unit,at word timings D₁ through D₁₄ under the normal display condition of thetimepiece. Output SRG-121 is used to transmit data from the shiftregister 1490 to the standard unit when alarm time data is beingdisplayed prior to setting in a new alarm time. For this reason thetiming of data from this output SRG121 OUT is one word time prior tothat of output SRG-111. Output SRG-441 is used to enable month and dateinformation sent from the standard unit to be compared with the datealarm data stored in shift register 1490. Output SRG-311 is used tocompare current time information from the standard unit with the hoursand minutes of alarm time stored in the option unit. Normally, with datais stored in serial form it is possible to process all data by taking asingle output from one stage of the shift register ring. However, sincewith this invention, the clock pulses are transmitted to the option unitin periodic bursts, the output circuits of the shift register must beaccordingly suitably designed and controlled. Data supplied from inputterminal DIN are written in to the 64 bit shift register ring 1490 viainput control gate circuit 1407, after passing through data demodulationblock 1409. Date circuit 1407 passes data into shift register ring 1490in accordance with input control signal SA generated by input datacontrol block 1403. Data outputs SRG-111 or SRG-121 of the shiftregister ring are designated D_(OUT), after selection by gate circuit1401, which controls Data output. D_(OUT) is connected to the DATA-INinput of the standard unit. Data in shift register ring 1490 is shiftedby clock pulses φ₁ * and φ ₂ *, generated from clock pulses φ₁ and φ₂from the standard unit by clock pulse control circuit 1408. It ispossible to increase the capacity of shift register ring 1490 byconnecting a 64(n-1) bit shift register between output terminal AXO andinput terminal AXI, where n is an integer.

Referring to FIGS. 27A, 27B and 27C, the option unit receives signalsfrom the standard unit at clock pulse input terminals φ₁ and φ₂, datainput terminal DIN, reference word timing pulse input terminal D₁₁,display selector pulse terminal D_(D), composite timing pulse inputterminals φ_(UC1) and φ_(UC2), manual shift signal input terminal MSINand DATA setting input terminal UDII. Output terminals D_(OUT) andC_(CL) of the option unit is connected to input terminals D_(IN) andD_(CL) of the standard unit. Various DATA can thus be exchanged betweenthe standard unit and the option unit through the respective input andoutput terminals.

The option unit also includes an output terminal FSO, which is connectedto input terminal FIN of the standard unit. After gain/loss compensationhas been initiated, pulses are sent from terminal FSO to compensate forerrors in the oscillator frequency of the standard unit. Output terminalAXO and input terminal AXI of the option unit permit the installation ofadditional shift register stages, enlarging the capacity for multi-alarmtime data storage in the option unit. Direct connection of theseterminals AXI and AXO allows up to four different alarm times of hoursand minutes to be set. This can be extended to eight alarm times byproviding an additional 64 bits, or sixteen by providing an additional256 bits of shift register storage capacity. It should be noted that,with more than sixteen alarm times, terminal CONT of the standard unitmust be set to the high logic level, so that clock pulses aretransmitted continuously to the option unit. Indicated by dashed linesin FIGS. 27A, 27B and 27C are connections which may be made to the"FLEXIBLE" circuit, mentioned previously, the gates and inverters ofwhich are shown here connected to form a voltage booster circuit. Theoutput Vss2 of this circuit is capable of applying a boosted voltage tothe display driver circuit at an efficiency of more than 95%. InputsφUC₁ and φUC₂ are applied as switching signals to the voltage boostercircuit.

Terminals Y_(SW) and X_(SW), shown in FIGS. 27A and 27B respectively,are preset to either the high or low logic level at the time ofmanufacture of the timepiece. If terminal Y_(SW) is set high, then thewearer can set in date data as well as hours and minutes data formulti-alarm times. If Y_(SW) is set low, then it is only possible to setin the hours and minutes data of alarm times. Terminal X_(SW) is used inpresetting an initial value into a counter in the automatic gain/lossadjustment circuits in manufacturing process, to be described later.

Input signals φ₁, φ₂ and D_(IN) of the option unit occur in periodicbursts if terminal CONT of the standard unit is set low, and aretransmitted continuously if this terminal is set high. The option unitis designed such that its operation is not affected, regardless ofwhether these signals are sent in bursts or continuously. Option unitinput signals D₁₁, φUC₁ and φUC₂ are always continuous.

Data applied from the standard unit to terminal DIN of the option unitis delivered to shift register ring circuit 1490 via data demodulatorblock 1409. The data demodulator block serves to eliminate the effect ofmodulation applied to all or part of the data to cause flashing of thedisplay.

The delivery of the data to the shift register ring 1490 is performedthrough gate 1407, controlled by command signal SA generated by datainput control block 1403. Either output SRG-111 OUT or SRG-121 OUT ofthe shift register ring circuit are selected and transmitted as outputD_(OUT) by output gate 1401. Gate 1401 is controlled by command signalsSB 1 and SB 2 from data output control block 1402. Output signal SB 3 ofcontrol block 1402 is transmitted from the option unit to the standardunit with the designation DCL. It's function is to cause erasure ofcertain alarm data when necessary.

The shift register ring circuit comprises a total of 64 bit shiftregister stages, and is capable of storing four different sets of alarmtime data, each consisting of four word times of DATA.

Shift register ring 1490 is periodically actuated to shift the datastored in it by bursts of clock signals φ₁ * and φ₂ *. These signals aregenerated by selectively gating portions of input clock signals φ₁ andφ₂ in clock control circuit 1408, under the control of clock commandsignal CONTφ. The latter is generated within the manual shift circuitblock 1420.

Input D₁₁ to the option unit is used as a reference timing signal withincircuit block 1430, to generate composite word timing pulses from inputsignals φUC₁ and φUC₂. The composite timing pulses can be represented bythe formula Q_(i) =D_(i) +D_(i+1), where Q_(i) is any one of thecomposite timing pulses Q₁ to Q₁₇. As already stated, signals φUC₁ andφUC₂ are also used in a voltage booster circuit.

Circuit block 1431, labelled TJ-RP-a, generates various combined bittiming signals, from inputs φ1 and φ2 and input φα+β from circuit block1430. Signals generated are T₂, T₄, T₈ and T₁, all of which have thesame phase relationships to the data words as the corresponding bittiming pulses in the standard timekeeping system, and also compositetiming pulses T₁₂ and T₂₄. T₁₂ is logically equivalent to T₁ +T₂, andT₂₄ to T₂ +T₄. The latter composite signals are produced in order tosimplify the interconnections within the integrated circuit.

Composite timing pulse generator TPG-a, block 1454, generates variouscomposite timing signals, from inputs Q₁ to Q₁₆, the bit timing signals,and synchronizing signals Φ₁ to Φ₄, to be discussed hereafter, as wellas clock signals φ₁ and φ₂. This block produces such composite signalsas Φ₃ D₁₁ T₈ φ₁. The timing of data interchange between the standardtimekeeping unit and the option unit under various conditions isbasically determined by control signals W_(KT), W_(DT), W_(AT1) andW_(AT0), generated by the WIDTH-a block 1451. Synchronization signals Φ₁to Φ₄ are generated within circuit block 1428. As stated previously, itis necessary to eliminate the effect of modulation applied to the datafrom the standard unit, i.e. modulation applied to the data or parts ofit so as to produce flashing on the display face of the timepiece. Itwould not be necessary to remove such modulation if a separateunmodulated data output terminal were provided on the standard unit. Inthe configuration described herein, however, this was not possible dueto practical limitations on the number of connections which can be madeto the integrated circuit chips. The function of the synchronization Φsignals is essentially to permit the modulated data to be processedwithin the option unit regardless of any flashing modulation which hasbeen applied. The circuit of block 1428 is shown in FIG. 34, and thewaveforms generated in FIG. 53. F1-phase waveform in FIG. 53 shows thetiming of modulation applied to the data from the standard unit to causedisplay flashing. As can be seen, the Φ signals are generated at timeswhen the data is unmodulated. They are produced from 1 Hz and 2 Hzsignals, which are generated by detecting the state of the seconds dataof current time in latch circuits actuated by timing pulses D₄ T₄ φ₁ andD₄ T₈ φ₁. (The current time data being one component of the data streaminput as D_(IN) to this circuit). Φ₄ is identical in waveform to Φ₃, butis delayed by one memory cycle with respect to it.

Circuit block 1429, labelled KT-DISP-DET-b, serves to detect thecondition that the timepiece is displaying current time. Output Q_(KT)from this block is applied to the automatic gain/loss adjusting block1480, as well as to the DT-DET-b block 1424 where it is used ingenerating a signal which erases the date data of a date alarm time whenalarm coincidence is detected.

Block 1427, AT-DISP-DETECT-b, detects the condition of alarm time beingdisplayed on the timepiece. If this condition is detected, signals areproduced which cause the stored alarm time data to be examined todetermine if a vacant alarm location exists. This process is actuated bysignals Q3AT 1 and Q3AT 2 going high, these signals being applied to theMAN-SHIFT block to control the timing of shift register clock pulseoutputs, and to the DATA-OUT-CONTROL block 1402 to control signals SAand SB, which switch the flow of data into and out of the option unit.

Alarm time coincidence detecting circuit AT-DET-b, block 1425 detectscoincidence between any alarm time stored in the option unit with thecurrent time applied thereto from the standard unit. The circuitAT-DET-b compares the data from output SRG 311 of the shift registerring 1490 with the current time and, upon coincidence being detected,immediately produces a signal initiating erasure of the correspondingalarm time data. This signal, QERAT, is generated within the same memorycycle. A coincidence detection signal designated DETAT is fed to anSRG-STOP block thereby stopping the operation of the shift register ring1490 for a fixed period.

Likewise, date alarm coincidence detecting circuit block DT-DET-bcompares the month and date data of stored alarm times with the currenttime day and date. A coincidence signal from this circuit erases thedata bit designated as a "connecting mark", which is set high for thehours and minutes data portion of a date alarm. The SRG-STP circuitblock 1426 generates an output signal Q_(STP), whose function is to haltthe operation of the option unit shift register ring for a period of oneminute. During this time, the standard unit functions as if it were notconnected to the option unit, and had only a signal alarm time storedwithin it. Q_(STP) is generated when alarm coincidence is detected, bysignal DETAT, or by signal O_(HAT) when an empty alarm data location hasbeen detected. Q_(STP) is reset to the low logic level by input Q₉ 60S↑or signal QΦ3 AT(2). Signal OHAT is generated by gate 1410, when anempty alarm data location occurs. When alarm coincidence occurs for adata alarm time, the month and date portion of this date alarm and theconnecting mark are automatically erased by circuitry in the standardunit.

Gate 1410 of OHAT-b is used to detect vacant data storage locations inshift register ring 1490, and send an output signal to the SRG-STOPcircuit. Whenever a vacant alarm time data location is generated, eitherby the wearer setting an alarm time of zero or by alarm coincidenceoccurring for a temporary alarm, then the hours portion of thecorresponding data in the shift register of the standard system is setto zero and the minutes portion is set to "all ones". The result is thatthe display then shows zero hours digits and a blank space in place ofthe minutes digits. When this data is transmitted to the option unit, itis necessary to reset the "all ones" state of the minutes data to zero,so that no errors will be caused when the "zero alarm time" data issubsequently sent back to the standard system. The "all ones" minutesdata is therefore detected by gate 1411, which generates a signalQ_(HER). This is sent to circuit 1405, and resets the minutes data tozero.

Manual shift circuit MAN-SHIFT-c 1420 applies a clock pulse controlsignal CONTφ to the clock control block 1408 so as to change therelative synchronization of the shift register ring circuit 1490 and theshift register ring circuit of the standard unit 58. Manual shiftcircuit 1420 also passes a control command signal MS↑ 2 to outputcontrol circuit 1402 to permit new alarm time data to be transferredfrom the option unit to the standard unit under manual control bysignals from terminal MSIN, which is connected to an alarm display shiftswitch.

Mark set block 1452 is used to set in mark bits which indicate, whetherthe alarm data to which they are connected is month/day or hours/minutsdata. These marks are set in accordance with the number of transitionsin the level of the UDII input. The mark set block 1452 also functionsto erase the alarm data stored in the option unit when necessary.

Signal MS↑ 1 is applied from the manual shift block 1420 to the mark setblock 1452 to set the count in a counter used for the abovementionedmark setting to zero.

An example of the multi alarm option circuit is illustrated in FIGS. 28Aand 28B. The shift register ring 1490 at the top of the drawingcomprises sixty four data-type flip-flops designated by numerals 111 to448. The shift register ring is shown as being interrupted at twoterminals Ax₀ and Ax₁. These are provided so that additional shiftregister stages 1494 may be connected if desired. The terminals Ax₀ andAx₁ are directly connected if shift registers 1494 are not used. OutputDOUT of the option unit is connected to terminal DATA-IN of the standardsystem whereas output DCL of the option unit connected to the terminalDATA CL of the standard system. (See FIGS. 11A and 11B) Terminal DATAOUT of the standard system is connected to input terminal DIN of theoption unit. Signals designated φ₂ * and CONTφ are available at outputterminals of the option unit, for use in other option units if required.The signals DIN, φ₁ and φ₂ will normally be sent in bursts, and thismust be borne in mind when examining how the option unit functions incombination with the standard system. The option unit is designed suchthat it operates irrespective of whether the signal mode is intermittentor continuous. The waveform of, input data signal D_(IN) is reshaped bypassage through two inverters in data processing block 1409, the passedto the shift register ring through input gate 1407. Gate 1407 iscontrolled by control signal SA, produced by data input control block1403. The input data is written into the shift register ring while SA ishigh in level. The stored data circulates around the closed ring 1490 ofshift registers when SA is low. Data from the shift register ringappears on outputs SRG-111 and SRG-121 either of which can be applied tooutput terminal DOUT via output control block 1401, whence it isconnected to terminal DATA-in of the standard system.

The output gate 1401 has control signals SB.sub. 1 and SB.sub. 2 appliedto it, generated by output control block 1402. Referring to FIG. 9 inthe description of the standard timekeeping system, it will be seen thatthe data at word reference timing D16 is designated at mark. The bits ofthis data word are used to indicate various characteristics of the alarmtime data. Bits T1 and T8 indicate AM/PM and daily/temporary alarm timedata respectively. If bit T4 is high, this causes the "alarm set" symbol(indicated as M_(AL) in FIG. 23) to be made visible on the display. If,when the timepiece is in the alarm setting mode with a multi-alarmoption facility, this symbol appears, this indicates to the wearer thatthe alarm storage location selected already contains alarm data.Accordingly, if it is desired to set in a new alarm time, the manualshift switch must be actuated to select a different alarm time storagelocation. When a vacant location is selected, the "alarm set" symboldisappears.

In the case of a date alarm, however, it is necessary for there to betwo sequential data storage locations vacant, to accomodate the fourwords of hours-minutes data and the four words of day-date data.Accordingly, in this invention, the circuit is arranged so that when thetimepiece is in the date alarm setting mode, then: (a) If the datalocation immediately subsequent to the location which has been selectedfor setting in the hours-minutes of a date alarm is already filled withdata, then an indication is given to the wearer that he cannot utilizethe location in question for a date alarm. This is done by setting bitT4 in the alarm mark word of the data selected for hours-minutes settingto the high level, causing the "alarm set" symbol to be displayed. Thishappens even if the location selected is vacant, so that zero hours andblank minutes digits appear on the display. (b) If the locationsubsequent to that selected for hours-minutes setting is vacant, and ifthe selected location is also vacant, then the "alarm set" symbol willbe blanked out, and alarm time zero will be displayed. This indicatesthat the hours and minutes of a date alarm can now be set iin.

For the subsequent date data, the bits of the alarm mark word are set asshown in Table IV, to be explained later. Bits T4 and T8 are set tozero, and T1 and T2 are set high. In this case, bit T₂ indicates to thedisplay decoding circuitry that a date alarm is to be displayed, causingthe appropriate date symbols to be displayed.

These mark bits are inserted into the alarm time data before it is sentto the standard system, by output control block 1401.

The shift register ring 1490 is driven by clock pulses φ₁ * and φ₂ *applied thereto from the controlled clock pulse generating block 1408.The clock pulses φ₁ * and φ₂ * consist of bursts of the clock pulsetrains φ₁ and φ₂ supplied from the standard unit, the bursts are timedto control the relative phase relation between data in the shiftregister ring 1490 and the shift register ring (64 bits) of the standardunit. The passage of the φ clock pulses is inhibited at the low level ofthe signal CONTφ.

The output control signal SB 1 generated by the output control block1402 selects signal SRG-111-OUT as data output by opening gate 1401,when data is transferred from the option unit to the standard system inthe normal time display mode. Signal SB 2 , generated in manual shiftoperation when the timepiece is put in the alarm time display mode,selects the SRG 121 stage as the source of output data from the optionunit. Signal SB 3 is the logical sum of SB 1 and SB 2 , and is used inerasing data stored in the shift register ring of the standard system.

Gates 1405 and 1406 connected to shift register ring 1490 are used insetting in the T2 and T4 bits of date alarm mark times, as describedpreviously. Owing to the short duration of the bursts of shift pulsesapplied to ring 1490, it is necessary to insert these mark bits insemi-parallel form utilizing two gates. Block 1404 is a gate circuitwhose function is to erase the month and day data of a date alarm timewhen data coincidence occurs, at 12.00 midnight when coincidence takesplace.

At thise stage in the description of the illustrated embodiment, it willbe advantageous to give some clarification of the timing relationshipbetween the standard system and the option unit.

When data is transmitted in burst form to the option unit, then it isapparent that the standard system and the option unit cannot operate insynchronism, strictly speaking. The data in the shift register of thestandard system circulated 256 times per second, and that in the optionunit only 16 times per second. Thus the two sets of data can only be incomplete synchronism once in every 16 circulations of the standard unit.Considering the standard system from the option unit, however, since the15/16 of a second during which the contents of the option unit shiftregister are static occurs between the end of a φ₁ clock pulse and thebeginning of a φ₂ clock pulse, there is in effect no loss ofsynchronism. Because of this fact, it is possible to examine theinteraction of the two units as if they were operating completely insynchronism, provided that clock pulses applied to the option unit, andnot seconds of absolute time, are used as the units of time.

In the illustrated embodiment, new alarm data stored in the option unitis transferred to the standard unit with the timepiece in the normalcurrent time display condition once in each memory cycle of the optionunit, that is, only once in every 16 memory cycles of the standard unit;the standard unit keeps circulating the alarm data thus applied theretountil the next set of data reaches it, that is, for 15 memory cycles. Ifterminal CONT of the standard unit 203 is grounded, setting it to thehigh logic level, clock pulses will be delivered from the standard unitin continuous mode, so that the standard unit and the option unitoperate in synchronism. This does not alter the operation of the system,however. In other words, the timing relationship between the standardunit and the option unit can be contemplated with the clock pulses astime base units, except for the mark formation in the output controlblock 1401. Here, bits D₁₆ T₂ and D₁₆ T₄ are inserted into the data sentfrom the option unit to the standard system, continuously. This isindependent of whether clock pulses and data are sent from the standardsystem to the option unit in bursts or continuously. In the standardsystem, as shown in FIG. 11A, output Q1 data singnal is used as a timingreference for the word timing pulse designations. But before this serialdata is sent to the option unit as DATA OUT, it passes through shiftregister stages 64 to 61 in the timekeeping register 64, then throughanother four shift register stages in delay unit 388 of the datamodulation unit (FIG. 20B). There is consequently a delay of eight bittimes or two word times between DATA OUT and the output Q1 of thetimekeeping register. Because of this, the standard system transfers thedata extending from the 1/256 second to the AT MARK data words duringthe word timing D3 through D16 to D2. This will be made clearer by thetiming chart of FIG. 51. Each word time designation for the option unitdescription corresponds exactly in terms of absolute time with thecorresponding word time of the standard system, i.e. D16 of the optionsystem corresponds with D16 of the standard system. It is necessarytherefore to pay careful attention to the difference of two word timingsbetween the data circulating in the standard system shift register andthe same data input to the option system.

When data is transferred from the option unit to the standard system,therefore is a delay of one word time between the data output from theoption unit and the corresponding data circulating in the standardsystem. Alarm time data is transferred from the option unit to thestandard system when signal WATI is high. Logically, WATI=D₁₅ +D₁₆ +D₁+D₂. Data is transferred from the standard unit to the option unit whenWATO is high. WATO=D₁₄ +D₁₃ +D₁₂ +D₁₁. Thus, both these timings differfrom the timing of the output of alarm data from Q1 of the standardsystem, which is D₁₃ +D₁₄ +D₁₅ +D₁₆.

Hereinafter will be described the various modes of data transfer betweenthe standard unit and the option unit.

(1) In the normal time display condition, a new set of alarm data istransferred from the option unit to the standard unit once in everymemory cycle of the option unit.

(2) In the alarm setting mode (in which alarm time data is displayed),the shift registers of the standard and option units are, in effect,held in synchronism. The same set of alarm data is then repeatedlytransferred from the standard system to the option unit and displayed onthe timepiece. Since the same data train is sent to the option unit asto the display unit, and since this data is normally modulated at a lowfrequency to cause flashing of certain parts of the displayed data,these transfers only take place when synchronizing pulse Φ₃ is at thehigh level. Φ₃ has a repetition frequency of 2 Hz, and as shown in FIG.53, only goes high when display flashing modulation is not beingapplied.

(3) With the timepiece in the alarm setting mode, with a multi-alarmoption facility, it is possible to change the alarm time data beingdisplayed to show all of the alarm times stored in the option unit. Thisis done by depressing the manual shift switch. This causes the alarmtime stored in the standard system to be transferred to the option unitshift register, in synchronism with Φ₃. Next, the data in the optionunit shift register ring is shifted by four words times with respect tothe timing of the standard system and transferred to the standard systemonce at the timing of MS 2 . The two shift register rings are then setback into synchronous circulation in the following memory cycle. Thus, anew set of alarm time data will now be continuously displayed. If theshift switch is held continuously depressed, the above sequence ofoperations will be repeated, so that a new alarm time is displayed every1/2 second.

(4) When the alarm time conincides with the current time in the normalcurrent time display mode data transfer from the option unit to thestandard unit is interrupted for 1 minute and, at the end of the 1minute is resumed.

(5) When the mode of operation is changed from the normal display modeto the alarm setting mode, the stored alarm time data is automaticallyexamined to detect a data location storing an alarm time of zero, i.e. avacant alarm location. If such a location is found, the zero data inthis location is transferred to the standard system, and the shiftregister ring in the option unit is halted, i.e. data circulation istemporarily stopped. The new set in alarm time data is then transferredfrom the standard system to the option unit, during synchronizationpulse Φ₃. This function is provided to enable new alarm times to be setin easily and quickly.

If no vacant alarm location is found, then the automatic search ishalted after 0.5 seconds, and the last alarm time set into the timepieceis transferred to the standard system. In this condition, to change thealarm time data displayed, it is necessary to actuate the manual shiftswitch, which generated signal MSIN. If this switch is depressed forlonger than 1 second, then automatic shifting of the alarm data begins,in which the stored alarm times are consecutively displayed at a rate ofone per second. This ceases when the shift switch is released.

(6) When the operating mode is returned from alarm display to normalcurrent time display, the alarm data which has been stored in thestandard system is first transferred to the option unit, duringsynchronizing pulse Φ₃, then the normal process of sequential transferof alarm data from the option unit to the standard system begins.

Regarding the provision of additional shift register stages, 1494 onFIG. 27A, where a large number of additional stages are added, it ispossible to connect the CONT terminal of the standard system to theunlock signal UL output. This means that continuous transmission ofclock pulses to the option unit only will occur during the setting in ofnew time data, and that burst transmission will be performed at allother times, thereby affording a substantial reduction in operatingpower.

Furthermore, if a calculator facility is provided, it is possible tosupply clock pulses to the calculator unit continuously when acalculation is being performed or data is being input, and send clockpulses in periodic bursts at other times, thereby ensuring a high speedof computation while power consumption is minimam. The ability totransmit and utilize clock pulses either continuously or in bursts makesfor unparalleled flexibility in any embodiment incorporating thetimekeeping system of this invention.

The operation of various circuit blocks which control the operation ofshift register ring 1490 will now be described.

Signal CONT φ, applied to clock control block 1408 in FIG. 27A, isoutput as CONT φ* from a first latch circuit in block 1408 at timing T8φ1, so that it is delayed by rather less than one word time before it isapplied as a gating signal for the φ₂ pulses. The logic product of CONTφ* and the φ₂ pulse train is designated φ₂ * and contains no transientspikes at the beginning and end of the gating period. The output of thesecond latch circuit referred to is further delayed by one bit time, andthis output is used to gate out timing pulses φ₁ *. The timing of CONT φmust therefore be one word time in advance of the timing for which aburst of φ* clock pulses is required. CONT φ is formed in circuit block1420, the manual shift circuit.

Input terminal MSIN of the manual shift circuit may be connected toterminal SUT or SU2 of the standard system. However in the embodimentdescribed herein MSIN is connected to a switch whose sole function is toshift the display of alarm time data, so that each of the alarm timesstored in the option unit may be examined by the wearer. Each time atransition from low to high logic level occurs on MSIN, a manual shiftsignal of approximately one memory cycle duration is generated,designated MS 1 ↑, in synchronism with timing pulse Φ₃. Signals MS 2 ↑and MS 3 ↑ are then consecutively generated at intervals ofapproximately one memory cycle. If terminal MSIN is kept continuously atthe high level for more than one second, then the sequence of shiftsignals MS 1 ↑ to MS3↑ is repetitively produced at a rate of one persecond. This ceases immediately MSIN is returned to the low level.

The timings of the bursts of φ₁ * and φ₂ * pulses for various operatingconditions are indicated by cross-hatched waveforms shown in FIG. 51.These timings are controlled by clock control block 1408 of FIG. 27A. Inthe normal time display operating mode, the φ* bursts are output fromword time D7 through D16 to D2. In the alarm display mode, they areoutput from D15 through D16 to D2. When a low-to-high transition of ofMSIN occurs during the alarm display mode, then in the following memorycycle a φ* burst is output from D14 through D16 to D1. In the memorycycle following that, the clock pulses are output for four word times,from D11 to D2. In the subsequent memory cycles the φ* bursts are againsent from D15 to D2, as long as the alarm display operating mode iscontinued.

Since signal CONT φ must be generated one word time in advance of theclock bursts which it controls, it is generated by word timing pulseswhose designating numbers are each one less than the correspondingnumbers for the clock pulse bursts. For example CONT φ is generatedduring times D6 to D1 to produce the φ* clock burst from D7 to D2 inFIG. 51.

Referring again to FIG. 51, the clock pulses applied to the shiftregister of the option unit in the normal time display mode occur inevery memory cycle for a duration of 12 word times, from D7 to D2,whereas the duration of a memory cycle in the standard system is 16words times. The result of this is that, each time the data in theoption unit shift register is shifted and a set of alarm time data sentto the standard system, a new set of data is sent, since the timingoffset of four word times between the two shift timing durationscorresponds to one set of alarm data. If the mode is changed from thealarm setting to the normal dispaly mode, then the shift register ringof the option unit can be considered as shifting data three times asquickly as in the alarm setting mode. If, therefore, the option unitdata is synchronized by the Φ₃ pulses in the alarm setting mode, it isalso synchronized by the Φ₃ pulses in the normal display mode. Thus, inthe alarm setting mode, the alarm data in the option and standardsystems is held in exact correspondence, and data set into the standardsystem will be transferred from the standard to the option unit duringsynchronizing pulse Φ₃. If, following the change of operating mode fromnormal time display to alarm display, a vacant alarm time location isdetected by gate 1410, then the option unit shift register circulationis stopped. After data designating a vacant location has been writteninto the standard system shift register, it is transferred to the optionunit, during pulse Φ₃ is in the "H" level. Since the repetitionfrequency of Φ₃ is 2 Hz, it follows that correspondence between thealarm data in the standard and option system will be established within0.5 seconds. Changes in the data transfer paths between the standard andoption units can thus take place without affecting the stored data, whenthe operating mode of the timepiece is changed.

When new alarm time data has been set into the standard system, it istransferred to the option unit every Φ₃ signal. When actuating themanual shift switch to cause a low-to-high transition of the MSINterminal of the manual shift circuit, the succeeding stored alarm timewill then be transferred to the standard system and displayed, and mayin turn be altered if so desired. The transfer of the newly set alarmtime from the standard system to the option unit takes place with timingD₁₅ to D₂, synchronized by timing pulse Φ₃, and the transfer of thesucceeding stored alarm time from the option to the standard systemtakes place from D₁₄ to D₁ in the following memory cycle of the optionunit. In the memory cycle following that, an extra burst of clockpulses, of four word times in duration, is applied to the option unitshift register. The result is that the alarm data in the option unitregister is in effect shifted relative to the standard unit shiftregister data by four word times. In the subsequent memory cycle, thesynchronous relationship between the option and standard unit shiftregisters is restored, but now with a different set of option unit alarmdata being in correspondence with that in the standard system. Theautomatic detection and display of vacant alarm time storage locationsdescribed in this embodiment is particularly useful when the number ofalarm times which can be stored is extended, by using additional shiftregister stages as described previously. When the operating mode ischanged from normal to alarm display, any vacant alarm location isimmediately displayed on the timepiece, so that the wearer can quicklyset in a new alarm time if so desired. If all alarm time locations arefilled, the wearer can select a time which is no longer required, byactuating the manual shift switch either in the step-by-step or thecontinuous shift modes. This type of automatic detection of vacantlocations is applicable to other types of option units, such as bloodpressure measurement and calculator options. The detection process canbe actuated by a switch signal generated when operation is changed fromthe normal time display mode to the particular option unit mode.

MARK-SET block 1452 is used mainly to generate signals to process dataalarm data. If terminal YSW, connected to this block, is set to the highlevel, then data alarm times can be set in, otherwise hours and minutesof alarm times can be simply set. A counter within the MARK-SET block isstepped by input signal UDII, which in the embodiment described hereincomes from the SU2 switch terminal of the standard system. Each time alow-to-high transition of the UDII input occurs, the bit timing sequencyof outputs ALI 1 , and ALI 2 , also ALD 2 of this block is changed, asshown in Table IV below. These signals are used, respectively, toinhibit and set data into gates 1405 and 1406 of shift register ring1409. The bit input at time D15T4 by ALD 2 indicates that a precedingalarm time data is connected to an immediately following date data. BitD2T2 set in by ALD 1 indicates that a symbol indicating date digitsshould be shown on the timepiece display when this data is displayed.

                  TABLE IV                                                        ______________________________________                                               D.sub.15  D.sub.2                                                      COUNT    T.sub.1                                                                             t.sub.2                                                                             R.sub.4                                                                           T.sub.8                                                                           T.sub.1                                                                           t.sub.2                                                                           t.sub.4                                                                           R.sub.8                              ______________________________________                                               ALD 2○                                                                           ALD 1○                                                                             ALD                                              0        0     0     0   0   0   0   0   0   (SHIFT                           1        0     0     0   0   0   0   0   0   REG.                             2        0     0     0   0   0   0   0   0   INPUT                            3        1     1     1   1   1   1   0   0   DATA)                            ______________________________________                                               ALI 2○                                                                           ALI 1○                                                                             ALI                                              0        0     0     0   0   0   0   0   0   (SHIFT                           1        0     0     0   0   0   1   1   0   REG.                             2        0     0     0   0   0   1   1   0   INPUT                            3        0     0     1   0   0   1   1   0   DATA                                                                          ENABLE                                                                        SIGNAL)                          ______________________________________                                               AT MARK OF                                                                              AT MARK OF                                                          PRECEDING FOLLOWING                                                           DATA      DATA                                                                (HOURS    (MONTH                                                              AND       AND                                                                 MINUTES OF                                                                              DAY OF                                                              DATE      DATE                                                                ALARM)    ALARM)                                                       ______________________________________                                         NOTE                                                                          1:H LEVEL                                                                     0:L LEVEL                                                                

Clock pulses corresponding to a duration of 4 word times are applied tothe shift registers of the option unit during setting of an alarm time.Thus, in order to set mark bits for hours-minutes and months-dates of adate alarm, pulses are applied to gates 1405 and 1406 of shift register1490 with the timing D₂ with respect to the currently displayed alarmtime data and with the timing of D₁₅ with respect to the alarm datastored subsequent to this displayed data. The signal QERAT applied tothe mark setting block 1452 is used to erase the alarm time data in theoption unit which has coincided with the current time in the standardunit. When an alarm time of zero is transferred from the standard unitto the option unit, the data corresponding to the 1-min. and 10-min.digits will be set to "all ones" state, to cause display blanking of theminutes digits. The signal QOHER resets these minutes data bits to thezero state.

Circuit block 1451 in FIG. 36 generates signals for determining thewidths of the control signals used for data transfer between the optionunit and the standard unit. As viewed in the circuit example of FIG. 36,signals WATO and WATI are produced with timings of from D₁₄ and from D₁₅to D₂, respectively, and are only when clock pulses are applied from thestandard unit. Signals WKT and WDT, on the other hand, designate thetimings at which data are transferred from the standard unit to theoption unit and are derived from a composite digit pulse which is inturn synthesized from boost continuous pulseses φUC₁ and φUC₂. Thus, thesignals WKT and WDT are free from the influence of intermittent clockpulses. These signals WKT and WDT are respectively used in thecontinuous form since no problems are raised from the viewpoint ofcircuit design.

Circuit block 1427 detects whether the timepiece is in the alarm displaymode, and generates control signals when this mode is detected. Inputsignal D_(D) is high during word time D₁₄ in the alarm display mode,whereas it is high during time D₆ in the normal time display mode. Allchanges in the condition of data transfer between the standard andoption units must take place during a Φ₃ pulse, as explained previously.The alarm display mode is therefore detected by applying the D_(D)signal to a latch circuit to which a clock input Φ₃ D₁₄ T₈ φ₁ isapplied. The output is latched into another latch circuit at time Φ₃ D₃T₈ φ₁. The output of the second latch is designated QΦ₃ AT 1 . Thissignal is applied to another latch circuit, and read out at time Φ₃ D₃T₄ φ₁ with the designation QΦ₃ AT 2 . This signal lags QΦ₃ AT 1 by 0.5seconds. These two signals are combined to form a logical product QA.These three signals QΦ₃ AT 1 , QΦ₃ AT 2 , and QA are used to cause thetransition from the current time display mode to the alarm time displaymode to be completed within 0.5 seconds after it is initiated by thewearer, with no transient effects on the stored data.

Circuit block 1429 detects the condition of display of normal currenttime, and outputs corresponding control signals, in precisely the sameway as for the alarm display detection, the only difference being in thetiming.

In circuit block 1425, coincidence between any of the alarm times storedin the option unit and the current time from the standard system isdetected. Upon coincidence, this circuit 1425 generates a signal toerase the alarm data itself during the same memory cycle. To do this, itis necessary to perform the comparison and erasure of the data duringD15 to D2. Referring to FIG. 42, it will be seen that the comparison isperformed by applying the standard system data DIN 3 and option unitdata SRG-311-OUT to an exclusive-OR gate, whose output is applied to thereset input of a bistable, during timing WKT, which is D7 to D10. Thisbistable is set by input Q4·Q_(A). If alarm coincidence occurs, thebistable will not be reset. In this case a logic product of the bistableoutput and signal WATl, which has timing D15 to D2, is generated asQERAT, and applied to a gate in block 1452 to cause alarm time dataerasure.

The month-day date alarm data detecting block 1424 is essentiallysimilar to alarm coincidence detector 1425. However, since the T₂ bit ofthe date mark word in the day-date alarm data is set high, it isnecessary to detect this date mark bit also, by ensuring that an alarmcoincidence output is only generated when the logical product of SRG-111OUT·D₁₄ T₂ φ₁ is low as shown in FIG. 43. The output of the block 1424is used to erase the day-date alarm data. In addition, the bits T₄ andT₈ of the connected alarm time data, immediately following, which havebeen set high to indicate that this data is the hours-minutes portion ofthe date alarm are also erased to zero. This alarm data is now in thesame form as any other simple hours-minutes alarm time, and coincidencewith current time will later be detected when it occurs that day.

It should be noted that, since bit T₂ of the mark word in the day-dateportion of a date alarm is set high, and bit T₄ of the hours-minutesportion of a date alarm is also set high, this data can never concidewith the current time sent from the standard system, since these twobits are always zero in the mark word of the current time hours-minutesdata.

Circuit block 1426 contains a bistable circuit, which can be set for aperiod of one minute, causing shifting of data in the option unit shiftregister to be stopped for the same period. When the bistable is reset,circulation of data in the register 1490 is again resumed. The bistableis set under two possible detection conditions. The first is, if avacant alarm data location is detected by the automatic search processwhen a wearer demands alarm time display. In this case, the bistable issubsequently reset by signal QΦ₃ AT 2 . The second case occurs when analarm coincidence is detected in the normal current time display mode.In this case, setting is actuated by signal DETAT from block 1425, attiming D₁₀ T₈ φ₂. The high level output of the bistable is read out froma latch circuit at timing D₃ T₈ φ₁ in the following memory cycle of theoption unit, and the output signal QSTP is applied to the manual shiftblock 1420 to stop the shift operation of the shift register 1490. Thebistable in block 1426 is reset one minute later by signal Q₉ 6OS↑ sentfrom circuit block 1483, and the shift register 1490 starts shiftoperation.

The data demodulator block 1409 processes the input data from thestandard unit in several ways. Data output DIN 1 is identical to datainput DIN, after waveform reshaping. Data output DIN 3 is applied to thealarm coincidence detection circuits previously described, and for thispurpose it is necessary to set bits T₂, T₄ and T₈ of the mark word inthe current time portion of the data to zero. This is done as shown inFIG. 30, by inhibiting the flow of data through a gate during word timeD10, except for bit T₁, which corresponds to the AM/PM data of thecurrent time.

Output DIN 2 only goes to the high level when the current time displaystate is detected. It is applied to the circuits used for automaticgain/loss adjustment, to be described later, to prevent any errors beingcaused in the date gate counter of these circuits, when setting in ofdata takes place.

Also in FIG. 30, the AND product D_(IN) 1 ·D₁₁ T₈ φ₁ goes to the highlevel when bit T₈ of the days-of-week data word goes to the high level.In the normal current time display mode, the days-of-week data displayis made flashing by a data moduration circuit in the standard system.When this flashing data of a day of the week is transferred to theoption unit, high level of Q_(FL) ·U_(DII) indicated that the timepieceis in the normal time display mode.

The relationship between the timings of the pulses Φ₁, Φ₂ and Φ₃ isshown in FIG. 53.

If desired, the circuit shown in FIG. 54 may be used an alternativearrangement for the gate 1463 shown in FIG. 46. Circuit block 1430,labelled Qi-RP-a, is used to generate composite timing signals Q₁ toQ₁₆, each of which has a duration of two word times and has the relationto the word time of the same numbering designation: Q_(i) =D_(i)+D_(i+1), where i is an integer from 1 to 16.

These Q pulses are produced based on the fact that signal φUC₁ is thelogical sum of the word pulses D₁ to D₁₆, and that φUC₂ lags φUC₁ by aperiod equal to the phase difference between clock pulses φ₁ and φ₂. Twosets of clock pulses, φα=φUC₁ ·φUC₂, and φβ=φUC₁ ·φUC₂ are thereforeapplied to shift a synchronizing timing word input D₁₁ along a set oflatch circuits which output signals Q₁ to Q₁₆.

As previously mentioned, shift register stages 1494 may be added toextend the number of alarm times which may be stored, if desired.Designated as 1480 is the automatic gain/loss adjustment section,consisting of circuit blocks 1481, 1482, 1483 and 1484. Block 1482 isthe date gate circuit. This contains a divide-by-eight counter which isused to perform a count from 0 to 7 days, i.e. one week, since thegain/loss calculation is performed over a period of one week. When thewearer initiates a gain/loss calculation, this counter is reset to zeroat just "0" second of the current time. Thereafter is begins to countthe number of days elapsed, by the input D_(IN) 2 . If the day on whichthe calculation was initiated is designated the first day, then on theeighth day following this (when the date gate counter has attained acount of 7), a gate is opened, as shown in FIG. 48 by output DGO fromthe date counter. Thus, when the wearer generates a UDII signal on theeighth day by depressing the appropriate switch, at precisely the "0"second of the current time on the eighth day (in response to, say, abroadcast time signal or a telephone service time information), thecalculation of time for gain/loss adjustment during the preceding weekwill be completed and an error compensating signal generated. If theswitch is depressed before or after the eighth day, then the datecounter is simply reset to zero, and the calculation process begins oncemore. This process is illustrated in FIG. 56, where the broad arrowsindicate the counter being advanced once per day by the current timedata, and the narrows indicate the step changes in count caused byswitch actuations.

In order to generate the signals which initiate and, after one week inreliable input operation mode, complete the gain/loss adjustmentcalculation process, the wearer must depress a switch in such a modedepressing (generating signal UDII) for more than 4 seconds and alsoless than 40 seconds, each time. This input condition is detected byidentification gate circuit 1483. If the switch is depressed for a timeduration within these limits, signal P₁ is output from circuit 1483exactly one minute after the switch is first depressed. FIG. 57 showsthe relationship between signal P₁ and switch input signal UDII.

Circuit block 1481 contains a divide-by 60 counter 1481K, whose count isheld constant during the week in which the gain/loss calculation isperformed, and another divide-by-60 counter 1481C which counts the unitsof seconds data of the kept time. Counter 1481C and the seconds count ofthe current time data kept in the register 58 in FIG. 3 are both resetto zero when the gain/loss calculation is initiated. Thus, at the end ofexactly one week, when the count of seconds for current time reacheszero, the count attained by 1481C, if other than zero, represents thetime gain or loss in seconds over the one week calculation period. As aresult, the count of the counter 1481K is added to the count of thecounter 1481C subtracted from the initial count stored within it in aweek. The outputs of counter 1481K, Q₃₁ to Q₃₆, serve to control theproduction of errorcorrection feedback pulses FSO, which are applied tothe timing pulse generator circuits of the standard system. A change of+1 in the count of 1481K causes the standard timekeeping system to gainan additional one second per week. To subtract the count in 1481C fromthe count in 1481K, a gate is opened at the completion of thecalculation period, by pulse P₁, which causes a high frequency pulsetrain of T₈φ to be simultaneously applied to the inputs of bothcounters. 1481C is thereby rapidly incremented until it reaches the zerocount state. This is detected, and causes the input pulse train to becut off, leaving counter 1481K with its initial count minus the initialcount of 1481C.

The circuit 1484 generates feed-back pulses at a rate depending on thecount in the counter 1481K. The feed-back signal is formed by combiningexisting timing pulses without using a frequency divider.

Assuming that the following logical relationships are true:

    8 Hz↑=B,

    Φ.sub.2 ·T.sub.12 ·T.sub.24 ·Q.sub.16 ·Q.sub.1 ·φ.sub.1 (≡BΦ.sub.2 D.sub.1 T.sub.4 φ.sub.1)=F.sub.1

    Φ.sub.2 ·T.sub.24 ·Q.sub.10 ·Q.sub.11 ·φ.sub.1 (≡BΦ.sub.2 D.sub.11 (T.sub.2 +T.sub.4)φ.sub.1)=F.sub.2

    Φ.sub.2 ·Q.sub.11 ·Q.sub.10 ·φ.sub.1 (≡BΦ.sub.2 D.sub.10 (T.sub.1 +T.sub.2 +T.sub.4 +T.sub.8)φ.sub.1)=F.sub.4

    T.sub.12 ·T.sub.24 ·Q.sub.16 ·Q.sub.1 ·φ.sub.1 (≡BD.sub.1 T.sub.2 φ.sub.1)=F.sub.8

    T.sub.24 ·Q.sub.16 ·Q.sub.1 ·φ.sub.1(≡ BD.sub.16 (T.sub.2 +T.sub.4)φ.sub.1)=F.sub.16

    Φ.sub.2 ·Q.sub.16 ·Q.sub.1 ·φ.sub.1 (≡D.sub.2 (T.sub.1 +T.sub.2 +T.sub.4 +T.sub.8)φ.sub.1 ·Φ.sub.2 ·B)=F.sub.32

and that the frequency of the signal FSO is fso and that of the signalF_(S1) is 0 Hz, then

F₁ : 1 Hz

F₂ : 2 Hz

F₄ : 4 Hz

F₈ : 8 Hz

F₁₆ : 16 Hz

F₃₂ : 28 Hz

Since the logical product of any two of the signals F₁ to F₃₂ is at alow level, frequency addition is possible when they are added logicallythrough an OR gate. The mean frequency fso of the signals Fso isexpressed as:

    fso=1/20(2.sup.0 ·Q.sub.31 +2.sup.1 ·Q.sub.32 +2.sup.2 ·Q.sub.33 +2.sup.3 ·Q.sub.34 +2.sup.4 ·Q.sub.35 +28·Q.sub.36) (Hz)

where Q₃₁ to Q₃₆ are either 0 or 1.

Addition of 1/20 Hz to the 32K Hz timekeeping clock frequency makes itpossible to causes a gain in time of about 1 sec. in a week, which meansthat the present system can compensate the weekly gain/loss error toless than 1 second.

The counts 33 to 59 in the counter 1465 can be used to designate thevalues -27 to -1 if the weight of the signal Q₃₆ is not 32 but -28.Since the low level of Q₃₆ indicates zero, the counts 0 to 59 in thecounter 1465 can be used as 0 to 31 and -28 to 31 1. Thus, output F₃₂ is28 Hz when signal Q₃₆ is at the low level.

Since part of the AND terms applied to gate 1484 in FIG. 49 is thecombination Q₂₁ ·Q₂₂ ·Q₂₃ ·Q_(KT) ·(Q₂₅ +Q₂₆), which goes to the highlevel only for 6 seconds in every 60 seconds, gate 1484 effectivelydivides the frequencies applied to it by a factor of ten. The signals Band Φ₂ have a common 1 memory cycle width and rise in synchronismalthough the frequency of the B signal is 8 Hz and that of the Φ₂ signalis 1 Hz. Thus, if the signal Φ₂ is added as a term of a logical productto the input of gate 1484 in FIG. 49, it is easy to provide division ofthe input frequency signals to this gate by the ratio 7/8.

In the following, details will be given of the operation of the variouscircuit blocks of the option unit shown in FIGS. 28A, B and C.

Referring to FIGS. 28A and B, details are shown of the shift registerring 1490 and associated gates. The shift register has 64 stages,identified by the numerals 111, 112, 114, 118, 121, 122 . . . , 448. Theshift register is driven by periodic bursts of clock pulses. The periodbetween each burst begins after a φ₁ phase clock pulse, and ends withthe application of a φ₂ clock pulse. Each stage of the shift registerring consists of a master-slave data type bistable, consisting of amaster latch circuit of dynamic type (in the sense that data written inby one clock pulse must be read out within a limited time by anotherclock pulse), and a static type slave latch circuit. Shift register ring1490 is equipped with a number of input and output terminals, to enabledata to be processed in a semi-parallel form, during the time intervalsin which the clock pulse bursts are applied.

While the alarm time stored in the standard system is being applied tothe option unit, during word timing D₁₅ to D₂, another set of alarm datais read out of shift register 1490 output terminal SRG-111. The datafrom the standard system is delivered to the option unit duringsynchronizing pulse Φ₃, as described previously. The Φ₃ pulses have aduration of one memory cycle, and a repetition rate of 2 Hz.

With the timepiece set to the alarm time display mode, each time amanual shift operation is actuated an alarm time, consisting of fourdata words, is transferred from the standard system to the option unit.Then, in the following memory cycle, a new set of alarm data istransferred from the option unit shift register to the standard unit.For each of these operations, a burst of clock pulses of four word timesin duration is applied to the 1490 shift register ring. For the first ofthese transfers (referring to timing chart FIG. 51), the burst is fromword time D₁₅ to D₂, and for the second transfer, from D₁₄ to D₁. Forthe first transfer, i.e. from the standard to the option unit, gatingcontrol in the option unit is by signal SA (from circuit block 1403 inFIG. 27B) going high. For the second transfer, from option to standardsystem, control is by signal SB2 generated by circuit block 1402 in FIG.27B. SB2 is generated in response to signal MS(2) from manual shiftblock 1420.

In the normal operating condition of displaying current time, bursts ofclock pulses of 12 word times in duration, from D₇ to D₂, are applied toshift register 1490. During each burst, four words of alarm time dataare transferred from the option to the standard system input terminalDIN. Since this output data must be in advance of the alarm time beingtransferred from the standard system to the option unit in the samememory cycle, by one word time, it is transferred from output SRG-121 of1490.

The current time hours and minutes data is input to the option systemduring timing D₇ to D₁₀. Alarm coincidence for this data is detected inblock 1425, by applying shift register output SRG-311 to this blocktogether with the current time data input DIN 3 . Coincidence of hoursand minutes data causes output QERAT to be generated by block 1425,which is applied to MARK-SET block 1452 generating signal ALI 1 . Thisin turn is applied to gate 1406 of the shift register ring 1490, causingerasure of the alarm time data for which coincidence has been detected.This erasure is performed during time D₁₅ to D₂.

The month and date data of current time kept in the standard system aredelivered to the option unit during word times D₁₂ to D₁₄. This datadiffers in phase from the date data of any date alarm time output fromSRG111 during the same time, by one word time. To perform a comparisonto detect coincidence of a data alarm time and the current data,therefore, output SRG-441 of shift register 1490 is applied to the datealarm time coincidence detection block 1424. On coincidence, signal ERDTis generated, which is applied to gate 1404 of the shift register ring,causing erasure of the month and date alarm time data for whichcoincidence has been detected.

It should be noted that the positioning of gate 1404 at the output ofstage 441 is important. As previously explained, the T₂ bit of the alarmmark word for date-month alarm data is set high, as is bit T₄ in thealarm mark word of the hours-minutes data immediately following it,thereby indicating that the two sets of alarm data are connected. Withthe arrangement shown, when date data erasure takes place, the T₂ markbit of the date data, and the T₄ mark bit of the following time data areboth erased to zero, together with the days-month data. Thehours-minutes data of the date alarm has therefore been converted intothe same format as any other hours-minutes alarm time, and can thereforebe detected for alarm coincidence. When coincidence occurs, this dataalso will be erased.

When a data alarm time is set into the timepiece, gates 1405 and 1406 ofthe shift register ring 1490 are used to insert the appropriate markbits into the stored data. Referring to Table IV, described previously,the "COUNT" column indicates the number of transitions of the UDIIsignal input to the counter of the MARK-SET circuit shown in FIG. 39.Inhibit signals ALI 1 and ALI 2 function to clear the bit locations ofthe data into which date alarm mark bits have to be inserted. On thefourth transistion of the UDII signal (i.e. the fourth time the wearerdepresses a corresponding switch), the bit codings for word times D₁₅and D₂ shown in Table IV are generated. Thus, high levels are set in forbit times T₂ and T₄ of the mark words for alarm time day-month data andthe connected hour-minute data, respectively, by ALD 1 and ALD 2 appliedto gates 1406 and 1405, respectively. (The corresponding bit locationshaving been set to zero immediately beforehand by signals ALI 1 and ALI2 . Any alarm time data set in under this condition is thereby stored asa date alarm.

The shift register ring 1490 also has a gate 1410 which is adapted todetect the zero digit of the alarm data in the option system. This gate1410 thus generates an output signal OHAT indicating that the hoursdigit of the alarm data is zero, i.e., vacant address. If the outputOHAT of the gate 1410 is read out at the timing of Φ₄ D₁ T₈ φ₁, it ispossible to detect that the shift register for the second alarm data isvacant. The gate circuit 1401 has a gate for the mark display, whichgates mark signal at the timing of D₁ T₄ Q_(A). When the following alarmtime is set and stored in the shift register, an alarm mark settingsignal is delivered to the display device to display the alarm settingmark. The gate circuit 1401 also has a gate to which the timing signalD₁ T₂₄ Q_(A) is applied to detect the date setting mark. An output isgenerated at the timing of D₁ T₂₄ Q_(A) and delivered to the displaydevice of the electronic time piece thereby to display the date markindicating that the date setting alarm is set.

The data applied to input terminal D_(IN) of the standard system attimings D₁ T₂ and D₁ T₄ is normally erased by gate 66 of the timekeepingregister 32 (see FIGS. 11A and 11B). However, it is possible to controlthe functions and display mode of the electronic time piece bypreventing this erasure, and continuously supplying timing signals D₁ T₄or D₁ T₂, thereby inhibiting the detection of coincidence between thecurrent time and the alarm time, or the timing signal D₁ T₂ for thedisplay of date indicating marks etc. to the D_(IN) input.

Gate 1411 serves to detect the state all ones i.e., (1,1,1,1) of theminutes of an alarm time to eliminate the malfunction of the displaygenerating by an output signal QOHER to erase the all ones state beforethe data is stored in the option system. In the event that alarm time isbeing displayed on the timepiece and the alarm data whose contents aredisplayed is "vacant," then the hours digit of the display shows "0",and the minutes data is shown "blank." This is caused by setting theminutes data to the binary code "1,1,1,1". The data is delivered back tothe shift register of the option system in this form. Subsequently, whenthis particular data is delivered back to the timekeeping register, ifnot erased, a carry condition will be detected, causing the ten minutesdata to be carried to the hours data by gate 68 of time keeping register32, so that the hours digit of the alarm time changes from "0" hours to"1" hour. The output signal QOHER from the gate 1411 is utilized toerase the "all ones" state of the minutes portion of "vacant" alarm datalocations in the option system. This is performed by gate 1404, inresponse to an inverted signal supplied from the mark setting circuit1452 generated by signal QOHER.

FIG. 30 illustrates an example of circuitry for data demodulatingcircuit 1409. An even number of inverters in this circuit serve toreshape the waveform of the input data, providing output signal D_(IN) 1which is applied to various parts of the option system such as gate1407, timing pulse generator 1454 and frequency adjusting circuit 1484.The demodulating circuit 1409 is arranged to detect the condition inwhich the days of week data is being modulated to cause displayflashing, and generate an output signal Q_(FL). This signal is appliedto an AND gate, which generates an output D_(IN) 2 when current time isbeing displayed and the days of week display is flashing. This outputsignal D_(IN) 2 is applied to the date gate 1482 so that the automaticadjustment of gain/loss is not adversely affected during setting of thedays of the week. The data demodulating circuit 1409 also generates anoutput signal D_(IN) 3 by erasing the D₁₀ T₂ to D₁₀ T₈ bits of theoutput D_(IN) 1 . Since these bits are only set high in the alarm markwords of the alarm time data, and are always zero in the current timedata, they must be reset before a comparison can be made between alarmtime and current time for alarm coincidence. Output D_(IN) 3 istherefore applied to comparison circuits 1425 and 1426.

FIG. 32 shows an example of a detail circuitry for the timing pulseregenerating circuit 1431. If the clock pulses φ₁ and φ₂ are in burstform, the output signals of the latches are affected so that the timingpulses T₁, T₂, T₄, T₈, T₁₂ and T₂₄ are output as burst signals, whichrise and fall in synchronism with the φ₂ clock pulses. The timing pulseT₁₂ is the logical sum of the timing pulses T₁ +T₂, and the timing pulseT₂₄ is the logical sum of the timing pulses T₂ +T₄. Since there is a agap between the fall of the timing pulse T₁ and the rise of the timingpulse T₂, the simple logical sum (T₁ +T₂) would be a discontinuouspulse, with adverse effects on the option system. To overcome thisproblem, the OR gate generating the sum is also supplied with a pulsewhich rises in response to the clock pulse φ₁ when the timing pulse T₁is at "H" level and which falls when the timing pulse T₂ is at "H"level, so that T₁₂ is generated as a single pulse. The timing pulse T₂₄is regenerated in the similar manner. The composite timing pulses T₁₂and T₂₄ are advantageous in that they enable the number of circuitconnections to be reduced.

FIG. 33 shows an example of circuitry for the current time displaydetecting circuit 1429, designated KT-DET-b. Signal D_(D), whichindicates the data being displayed, indicates current time display whenD_(D) =D₆, the date display when D_(D) =D₁₁, and the alarm time displaywhen D_(D) =D₁₄. Thus, the current time display detecting circuit 1429is supplied with the signal D_(D) as a latch input, which is latched atthe timing of D₆ to detect the condition of current time beingdisplayed.

FIG. 35 shows an example of a detail electric circuitry for the alarmtime detecting circuit 1427, designated AT-DISP-DET-b. Similarly to thecurrrent time detection, the condition of alarm time being displayed isdetected at the timing of D₁₄ by a latch circuit with the input D_(D).The condition of alarm time being displayed means that a new alarm timecan be set in. In this condition, it is necessary to maintain thesynchronized relationship between the electronic time piece and theoption system, to ensure that signals are exchanged with completereliability. To this end, the display condition is detected at thetiming Φ₃ D₁₄ T₈ φ₁ causing an output signal to be generated by a firstlatch circuit. This output signal is applied to a second latch circuitand read out at the timing of Φ₃ D₃ T₈ 100 ₁, designated as Q.sub.Φ3AT1.This output is applied to a third latch circuit and read out at thetiming Φ₃ D₃ T₄ Q₁, designated as Q.sub.Φ3AT 2 . The output signalsQ.sub.Φ3AT 1 and Q.sub.Φ3AT 2 are applied to an AND gate, whose outputsignal Q_(A) indicates that alarm data is being displayed. The outputsignals Q₁₀₁ 3AT 1 and Q₁₀₁ 3AT 2 are applied to the shift registerstopping circuit 1426, to detect a vacant shift register, alarm locationduring the setting of the alarm time, in a manner which will besubsequently described in detail. The logical product of the outputsignal Q.sub.Φ3AT 1 and the inverted output signal Q.sub.Φ3AT 2 ,syncrhonized with the pulse Φ₃, is maintained in "H" level for a halfsecond indicating that an alarm time is set.

FIG. 36 shows an example of detail circuitry for the pulse generatingcircuit 1451, designated WIDTH-a, used to generate signals W_(KT),W_(DT), W_(ATO) and W_(ATI). The signals W_(KT) and W_(DT) correspond tothe timing of the current time data and date data in the output from thestandard system, W_(KT) and W_(DT) are produced by a logic summing gatein accordance with the following equations:

    Q.sub.7 +Q.sub.9 =D.sub.7 +D.sub.8 +D.sub.9 +D.sub.10 =W.sub.KT

    Q.sub.12 +Q.sub.13 =D.sub.12 +D.sub.13 +D.sub.14 =W.sub.DT

The pulse generating circuit 1451 also generates timing signals W_(AT0)and W_(AT1). The timing signal W_(AT0) is utilized for opening a gatewhich transmits signals from the option unit to the standard system, andthe timing signal W_(AT1) is utilized for opening a gate which transmitsdata from the standard system to the option unit. These timing signalsare required to be generated in bursts modulated when the clock pulsesφ₁ and φ₂ and the timing pulses T₁ to T₈ occur in bursts. Likewise, thetiming signals W_(AT0) and W_(AT1) are required to be continuous whenthe clock pulses φ₁ and φ₂ are continuous. To this end, the pulsegenerating circuit 1451 includes a bistable which generates a burstcontrol signal which rises in synchronism with Q₁₄ ·T₁₂ and falls insynchronism with Q₃. This signal is applied to gates by which two burstsignals W_(AT0) and W_(AT1) are produced in response to the signals Q₂and Q₁₃, respectively. W_(AT0) rises in synchronism with the rise of theword timing pulse D₁₄ and falls in synchronism with the falling edge ofthe word timing pulse D₁. The timing signal W_(AT1) rises in synchronismwith the rising edge of D₁₅ and falls in synchronism with the fallingedge of D₂.

FIG. 41 shows a preferred example of circuitry for the data outputcontrol circuit 1402 which generates signals SB.sub. 1 , SB.sub. 2 andSB.sub. 3 , which control the transmission of data from the option unitto the D_(IN) input terminal of the standard system in syncrhonism withthe pulse Φ₃. The data output control circuit 1402 contains a gate whichdetects the normal current time display state i.e., Q₁₀₁ 3AT 2 ="L" andthe state in which the shift register is not stopped, i.e., Q_(STP) =0,to generate SB1, SB1 causes the data from output SRG-121 of the shiftreigster ring 1490, (which is delayed by one word time with respect tooutput SRG-111) to be delivered to terminal D_(in) of the standardsystem at timing D₁₄ to D₁. Note that this timing is one word time inadvance of the timing of alarm data output from the standard system. Thedata output control circuit 1402 also contains a gate which generates asignal SB2, in response to input signal MS2. This controls thetransmission of data from the output SRG-111 of shift register 1490 tothe standard system during timing D₁₄ to D₁ each time the manual shiftswitch is actuated t delivr a new set of alarm time data stored in theoption unit to the standard timekeeping system. The data output controlcircuit also has a gate which generates a signal SB3 when SB1="H" orSB2="H". SB 3 is delivered to the DCL terminal of the standardtimekeeping system to reset the alarm time data stored therein to zero.

FIG. 40 shows a preferred example of circuitry for the data inputcontrol circuit 1403, designated S_(A) -C, used to generate a signal SA.Data from the standard timekeeping system is delivered to the optionunit through gate 1407 when SA="H". SA is generated by a gate inresponse to signal W_(AT1), i.e., during timing D₁₅ to D₂, when alarmtime data is delivered from the standard timekeeping system after a halfsecond has passed following the alarm time being set, i.e., QA=Q_(3AT) 1·Q_(3AT) 2 ="H" and in response to pulse Φ₃. SA is applied to gatecircuit 1407, which gates through all the data except bits T₂ and T₄ ofword D₂ i.e., data including the daily/temporary mark bit for the alarm,AM/PM mark bit and digits of hours, 10 minutes and one minute. WhenSA="L", however, the shift register ring 1490 is closed to form a ringcircuit in which the stored data is shifted.

FIG. 34 shows a preferred example of circuitry for the pulse generator1428, designated Φ-GEN-a. The standard timekeeping system and the optionsystem are synchronized with each other by signal Φ₃ generated by thiscircuit. Φ₃ has a pulse width equal to one memory cycle and being insynchronism with the falling edge of the 2 Hz signal, as shown in FIG.53. The D_(IN) 1 signal is applied to a first latch circuit, and islatched at timing D₄ T₄ φ₁ to generate a 2 Hz signal from the secondsdata of the current time. This 2 Hz signal is applied to a second latchcircuit and latched at timing D₄ T₂ φ₁. The inverted output signal Qfrom the second latch circuit, together with its input signal, areapplied to a gate which generates a signal Φ₃ synchronized with thefalling edge of the 2 Hz signal. In this illustrated example, the wordtiming pulse D₄ is applied to the gate as an inhibit signal, so that Φ₃rises in synchronism with the rising edge of word pulse D₅ and falls insynchronism with the falling edge of the word pulse D₃. The D_(IN) 1signal is also applied to a third latch circuit and latched at thetiming D₄ T₈ φ₁ so that a 1 Hz signal is generated. This 1 Hz signal isapplied to a second gate which generates a signal Φ₂ following thetransition of the 1 Hz signal to the "L" level, i.e. during the counts 0to 0.5 seconds of the current time. The 1 Hz signal is also applied to afourth gate which generates a signal Φ ₁ following the transition of the1 Hz signal to the "H" level, i.e., during time counts 0.5 to ;b 1seconds. Φ₃ is applied to a fourth latch circuit and latched at thetiming D₃ T₈ φ₁ so that a signal Φ₄ is generated, delayed by one memorycycle from the signal Φ₃. Φ₄ is utilized for detecting vacant locationsin the shift register 1490. As shown in FIG. 53, signal Φ₃ has a 2 Hzrepetition frequency, and is timed such that it is not affected bymodulation of data output to the display unit from the standard timekeeping system, and occurs just after each change in the seconds data ofcurrent time. Output data from the standard timekeeping system istherefore read into the option unit circuits in synchronism with Φ₃, inorder to utilize data which is not affected by the display modulation.It is to be noted that since the period of Φ₃, 0.5 seconds, is a commonmultiple of the time required for one cycle of the data in the shiftregister ring of the standard timekeeping system and also of the timerequired for one cycle of the data in the shift register ring of theoption system, the relative phase of data in the shift registers of thestandard timekeeping system and the option system are constant withrespect to pulse Φ₃.

In FIG. 44, there is shown a preferred example of detail circuitry forthe shift register stopping circuit 1426, used to generate a signalQ_(STP) for stopping the shifting operation of the shift register ring1490 under the following conditions:

a. when the hours data of the alarm time is zero, i.e., when OHAT·D₁ T₈φ₁ ="H" during the time period of 0.5 seconds when Q₁₀₁ 3AT 1·Q.sub.Φ3AT 2 ="H", i.e., during the time period in which the search fora vacant shift register location is automatically performed just afterthe alarm time has been displayed; and

b. when the alarm time data coincides with the current time, (i.e., whenD₁₀ T₈ φ₂ ·DETAT="H"), in the normal correct time display condition(Q.sub.Φ3AT 2 ="L").

The shifting operation of the shift register ring 1490 is started by thesignal Q.sub.Φ3AT.sbsb. 2 when 0.5 seconds have passed after theinitiation of alarm time display, i.e., when Q₁₀₁ 3AT.sbsb.2 ="H". Ifthe alarm time data coincides with the current time, the shiftingoperation of shift register ring 1490 is stopped in the followingmanner. Alarm time coincidence which occurs with the timepiece in thenormal current time display mode is detected at timimg D₁₀ T₈ φ₂. Thealarm time data for which coincidence has occurred is delivered from theoption system to the standard timekeeping system at timing D₁₄ to D₁. Asthis alarm time data is output from the fourth stage of the shiftregister after the input, it is erased during timing D₁₅ to D₂.Therafter, the clock pulses φ*₁ and φ*₂ are inhibited from beingsupplied to shift register ring circuit 1490 so that the shiftingoperation thereof is stopped. Shifting is started again after 60 secondshave passed following alarm coincidence, by the signal Q₉ 60S↑. Thesupply of the clock pulses φ*₁ and φ*₂ is stopped during timing of D₃ toD₆ for the normal time display condition, and during timing D₃ to D₁₄for the alarm time display condition. The signal controlling φ* isgenerated by a latch circuit in response to the signal D₃ T₈ φ₁.

FIG. 43 illustrates a preferred example of detailed circuitry for thedate alarm data coincidence detecting circuit 1424, used to generate asignal ERDT. The data output SRG-441 and the signal D_(IN3) are comparedduring three word times, D₁₂ to D₁₄. If date coincidence occurs, themonth and date data of the alarm time and the connecting bit of thepreceding alarm time are erased during the four word times D₁₅ to D₂.Lack of coincidence between the month and date data of the alarm timeand the month and date data of current time is detected during thetiming D₁₂ to D₁₄, i.e., when W_(DT) ="H". In addition, the "H" level ofthe date mark bit i.e., bit T₂ of the mark word of the month and datedata of a date alarm time is detected by gating the data from outputSRG-111 at time D₁₄ T₂ φ1. If at least one of the signals goes to "H"level, the bistable, which had been set at timing D₄ if the timepiece isin the current time display mode, is reset. The signal ERDT is thelogical product of the output of the flip-flop and the signal W_(ATI),thus if coincidence occurs it goes high for timing D₁₅ to D₂ and is usedto erase the month and date data of the alarm time, as well as theconnecting mark of the hours-minutes portion of the alarm time, by gate1404 of shift register ring 1490.

FIG. 42 shows a preferred example of detailed circuitry for the alarmtime coincidence detecting circuit, used to generate a signal to erasehours-minutes alarm time data when this data coincides with currenttime. The current time data is applied as input D_(IN) 3 to anexclusive-OR gate together with data from output SRG-311 of shiftregister ring 1490, to perform alarm coincidence comparison. The outputof the exclusive-OR gate is detected during the timing D₆ to D₉, i.e.when W_(KT) ="H". If, coincidence does not occur during this time, abistable is reset by the output of the exclusive OR gate. If, on theother hand, the alarm time data coincides with the current time data,the output of the bistable will be "H" during time period D₁₀ T₁ to D₄.The output of the bistable is applied to an AND gate, to which an inputW_(ATI) is also applied, so that an output signal Q_(ERAT) is generated.This output signal is applied to the mark setting circuit 1452 whichconsequently generates an output signal ALI.sub. 1 . This is applied tothe gate 1406 of the shift register ring circuit 1490 thereby erasingthe alarm time data. The output DETAT of the bistable is applied to theshift register stopping circuit 1426.

FIG. 38 shows a preferred example of detailed circuitry for the manualshift circuit 1420. The control is such that when normal current time isdisplayed, a new set of alarm time data is delivered to the standardtimekeeping system in each memory cycle is updated, whereas when alarmtime is displayed, the alarm time data being displayed can be replacedby new alarm time data, in response to a command signal generated byactuation of the manual shift switch. In the normal current time displaymode, signal Q_(A) is in the "L" logic state. Since it is applied to aninverting input of an AND gate together with timing signals Q₄ and Q ₂,an output is generated in this condition which rises with the risingedge of word pulse D₆ and falls with the falling edge of D₁. Thisoutput, designated CONT φ, causes clock pulses φ₁ * and φ₂ * to begenerated for the timing of word pulses D₇ to D₂ through D₁₆, as shownin timing chart FIG. 51.

Terminal MSIN of manual shift circuit 1420 is connected to an externalcontrol member such as manual shift switch 266 in FIG. 18. With thisswitch released, terminal MSIN is held at the "L" level by reset pulsesD₂ T₈ φ₁, but when the switch is depressed, MSIN is set to "H" level. Ifthis "H" level is maintained for a time interval of more than onesecond, then when QΦ,_(3AT) 2 goes to "H" level in the alarm timedisplay mode the "H" level of input terminal MSIN is latched into afirst latch circuit at timing Φ₃ D₃ T₈ φ₁. Gate 1422 thereby generatesan MSIN signal. The output of the first latch circuit is latched into asecond latch circuit at timing Φ₃ D₃ T₄ φ₁ so that an output signaldelayed by about one second with respect to the start of the MSIN "H"state is generated. The output signals from the first and second latchcircuits are applied to AND gate 1421, to which the input signal to thefirst latch circuit and the signal Φ₂ are also applied, so that outputsignal MS↑ 1 is generated. When the input terminal MSIN is returned tothe "L" level, a new alarm time is displayed. This will be referred toherein as manual sweep operation. The bistable which stores the manuallyset MSIN input is normally reset by a signal which is the logicalproduct of the signal Φ₃ and the signal D₃ T₈ φ₁. If input terminal MSINis set to high level when Φ₃ is at "L" level the bistable is set andreset again by the signal Φ₃ D₃ T₈ φ₁. The logical product of the outputof the bistable in its set condition and signal Φ₃ is a signal which ineffect detects the high level state of input terminal MSIN insynchronism with signal Φ₃. When the outputs of the first and secondlatch circuits are at low level, the high level MSIN input is applied tothe gate 1422 as a manual sweeping input. The output signal MS↑ 1 isdelayed by a third latch circuit at the timing of D₃ T₂ φ₁ by one memorycycle and a signal MS↑ 2 is generated. The signal MS↑ 2 is utilized fordelivering a new set of alarm time data from the option system to thestandard time keeping system in the memory cycle just after the manualshift operation. Since, in this instance, it is necessary to supplyclock pulses φ*₁ and φ*₂ into the shift register ring circuit 1490 forthe 4 word times between D₁₄ to D₁, the signal CONT φ causes φ* pulsesto be generated for these times when MS 2 ↑ is at the "H" level. MS 2 ↑is supplied to a fourth latch circuit by which it is delayed by onememory cycle, at the timing D₃ T₁ φ₁, generating signal MS 3 ↑. When MS3 ↑="H", the signal W_(ATO) (which rises in synchronism with the risingedge of word timing pulse D₁₄ and falls in synchronism with the fallingedge of word timing pulse D₁) and a signal which rises in cynchronismwith the rising edge of word timing pulse D₁₀ and falls in synchronismwith the falling edge of the word timing pulse D₁₃ are summed togenerate signal CONTφ. In this case, φ* clock pulses are generated forthe word times D₁₁ to D₂, as shown in FIG. 51, i.e. for eight wordtimes. As stated previously, when bursts of φ* clock pulses are sent forfour word time periods per memory cycle in the alarm setting mode, theshift register rings of the standard and option systems are effectivelyheld in synchronism. The extra set of φ* pulses, of duration four wordtimes, generated when the MS 3 ↑ signal occurs, cause the data in theoption and standard system shift registers to be shifted with respect toeach other by four word times, i.e. by one set of alarm time data. Thus,the next time the manual shift operation is performed, a new set of datais sent from the option to the standard system. The signal MS 1 ↑ issupplied to the mark setting circuit 1452, causing a mark settingcounter to be reset to zero so that the mark data newly stored in theoption unit shift register ring circuit by the manual shifting operationis not altered. The manual shift circuit 1420 is supplied with signalQ_(STOP), which is synchronized with signal D₃ T₈ φ₁, from the shiftstop circuit 1426. This controls the supply of φ* clock pulses from themanual shift circuit. With the manual shifting circuit 1420 thusarranged, the shift register ring circuit 1490 is not supplied withclock pulses during word times D₃ to D₆ in the normal current timedisplay mode. Thus, in this operating condition, the data stored in theoption system is, in effect, delayed by 16 bits, i.e. four word times,in each memory cycle, relative to the data stored in the standardsystem. The result is that, during timing D₁₄ to D₁ of each memory cyclea new set of alarm data is transferred from the option unit to thestandard system.

When alarm time is displayed, however, the data stored in the optionsystem is, in effect, advanced by two word times each memory cyclerelative to the data in the standard system. Since the alarm data in theoption system is delivered back to the standard system twice per secondwhen signal Φ₃ is high, and since the period of Φ₃, 1/2 second, is aneven factor of the time for once cycle of data stored in the standardsystem, then insofar as data transfer from the option to the standardsystem is concerned the two shift register rings of the option andstandard systems are circulating in synchronism.

FIG. 39 shows a preferred example of detailed circuitry for the marksetting circuit 1452. As shown, the mark setting circuit 1452 includestwo bistables, constituting a mark setting counter. As already mentionedhereinabove, the alarm time data is shifted and displayed by the manualshifting operation. If, in the alarm display mode, the switch connectedto the UDII input terminal is depressed three times, mark settingcircuit 1452 generates signals ALI.sub. 1 , ALD.sub. 1 , ALI.sub. 2 andALD.sub. 2 as shown in Table IV. These insert the month-date alarm markand the hours-minutes connecting mark by which the detection ofcoincidence between the alarm time data and the current time data isinhibited. The mark setting counter is reset by any of the following: MS1 ↑ signal occurring, the condition of the alarm time not being set orterminal Y being set low. When Y is set to "L" level the mark settingcounter is fixed in the reset condition so that it is impossible to setin date alarm times. If the counts 0, 1, 2 and 3 of the mark settingcounter are designated N₀, N₁, N₂ and N₃, following equations hold:

    ALD.sub. 2 =N.sub.3 ·Φ.sub.3 D.sub.15 T.sub.4

    ALI.sub. 2 =(N.sub.1 +N.sub.2 +N.sub.3)·Φ.sub.3 D.sub.15 T.sub.4 +Q.sub.16 ·QOHER

    ALD.sub. 1 =N.sub.3 ·Φ.sub.3 D.sub.2 T.sub.2

    ALD.sub. 2 =(N.sub.1 +N.sub.2 +N.sub.3)·Φ.sub.3 D.sub.2 T.sub.24 +QERAT.

Referring now to FIG. 46, a preferred example of detailed circuitry ofthe date gate 1482 is shown. The date gate 1482 contains a counter 1467which is used to count the days of the week to 8 (0-7). When the count 7is detected from the counter 1467, a trigger input pulse is applied to asecond counter, which is a single bistable stage. When the count 8 isoutput by the first counter 1467, it is reset to "0", and the secondcounter is set to "1". In this condition, the count input to the firstcounter 1467 is inhibited. When DGO="H" (i.e., DGO="L"), the firstcounter 1467 counts to 8 and, in this condition, the date gate isopened. The first counter 1467 is reset by an input signal DG-reset,which will later be described in detail and a computing start signalfrom a gate 1462, which the second counter is reset by the input signalDGR. As shown, the date gate circuit 1467 also has a gate 1463 whichdetects the falling edge of the signal indicating a change of the AM/PMdata. The output of this gate is applied to the first counter as aninput.

FIG. 48 shows a preferred example of detailed circuitry for thecomputing circuit 1481. Computing circuit 1481 contains a first counter1465 and a second counter 1466, both of which count to 60 (0-59).Computing circuit 1481 also includes first and second bistable 1471 and1472 which are connected to the first and second counters 1465 and 1466,respectively. The condition of a count of more than 60 is memorized inbistables 1471 and 1472, and the outputs of these bistables are appliedto the reset inputs of counters 1465 and 1466, respectively, to resetthem to "0". The computing circuit 1481 has an input terminal X which isnormally set to a "L" level. When X is at "H" level (to set thegain/loss circuit in the factory) the outputs of the flip-flops 1471 and1472 are applied to the first and second counters 1465 and 1466, whichare consequently reset to "0". The computing circuit 1481 also includesa third bistable 1473 which is set by the logic product of the invertedsignal DGO from the date gate circuit 1482 and the calculating commandsignal P₁ delivered from the input analyzing circuit 1483.

The computing circuit also has a gate 1461 to which signals Φ₃ D₃ T₈ φ₁and Φ₁ are applied so that a 1 Hz signal synchronized with the timing T₈φ₁ is generated. Signals T₈ φ₁ and Q_(C) are applied to gate 1462, whichgenerates a 64 Hz signal. This is applied to the first and secondcounters 1465 and 1466 when bistable 1473 is set. This signal is alsoapplied to a gate which generates a DG-reset signal to be applied to thereset input of the counter 1467 of the date gate circuit 1482.

If the switch is depressed to set terminal UDII high and activate thecomputing circuit 1481 when DGO ="H", then a P₁ input signal isgenerated after one minute has passed following depression of theswitch. Since actuation of the switch automatically zeros the seconds ofcurrent time data in the standard timekeeping system and simultaneouslyresets first counter 1465 of computing circuit 1481, the seconds counterof the standard timekeeping system coincides and counter 1465 of thecomputing circuit 1481 will then begin counting seconds simultaneously.In this condition, with the count in each of the counter "O", the dategate counter 1467 is reset by P₁, through DG-reset. If the next inputsignal P₁ is generated one week later, when DGO="H", bistable 1473 ofcomputing circuit 1481 is set and generates a signal Q_(C), i.e., Q_(C)goes to "H" level, and consequently, the counts in the first and secondcounters 1465 and 1466 are shifted at a high speed by signal T₈ φ₁applied via gate 1462. Thus, the count in counter 1465 quickly goes to"O". This resets bistable 1473 to "O" and since Q_(C) is now low, gate1462 is closed, and the new count of counter 1466 is left storedtherein. The reset signal DG-reset is also applied to the date gatecounter 1467 of the date gate circuit 1482 so that output DGO goes tothe high level. We may designate the count in the second counter 1466,the first time input signal P₁ is applied, as K₁. Count C₁ of the firstcounter 1465 is zero after input signal P₁ has been applied for thefirst time. We may also designate the count in the first counter 1465after P₁ is generated for the second time, as C₂, this means that theelectronic timepiece in the illustrated embodiment has gained C₂ secondsin one week. The second time input signal P₁ is applied to bistable1473, the output signal Q_(C) goes to the high level and, therefore,(60-C₂) number of pulses are applied to counter 1466 which consequentlycounts to the value (K₁ +60-C₂). Since counter 1466 is of the type inwhich overflow occurs when the calculated result exceeds the count of60, the resultant count in the counter 1466 is (K_(1-C) ₂). The circuitarrangement is such that a correcting signal is generated to cause again in time of one second in a week for each unit increment of thecount in counter 1466. So, since C₂ has been subtracted from the countstored in counter 1466, the gain of C₂ second which has occurred in oneweek will be exactly compensated for.

Referring to FIG. 47, a preferred example of circuitry for the inputanalyzing circuit 1483 is shown. The input analyzing circuit 1483includes a gate which generates an output signal in response to thelogic product of signals UDII and QKT. This output signal is applied toan inverter 1464 which generates an output signal UDII*. This outputsignal is applied as an input signal to a first latch circuit andlatched by composite digit signal Q₆. The inverted output of the firstlatch circuit and the output UDII* are appled to a gate, by which ashort pulse is generated, which rises in synchronism with the leadingedge of output UDII*. This pulse is applied to the reset input of anedge-triggered bistable. The non-inverted output of the first latchcircuit is applied to a second latch circuit. Here, it is latched insynchronism with the "four seconds" bit of the current time data, by thesignal Φ₃ D₅ T₈ φ₁.D_(IN2). Let us assume that the state UDII="H"continues for a time interval beyond four seconds. In this instance, thesecond latch circuit detects that the four seconds bit has gone to thehigh level while input UDII* applied to the first latch circuit is heldat high level. The result is that the inverted output Q of the secondlatch goes from high level to low level so that the edge-triggeredbistable is set and consequently generates an output of high level. Inother words, if the state UDII*="H" is continued for a time intervalbeyond four seconds, the gain/loss adjusting signal is stored in thisbistable. If the signal UDII* becomes low level after, a time intervalof more than four seconds has elapsed, signal DIN2 is latched into athird latch circuit by the signal Φ₃ D₆ T₄ φ₁, in synchronism with thebit representing 40 seconds in the current time. Thereafter, the changesin minutes data of the current time kept in the register 58 in FIG. 3represents the falling edge of the 40 seconds signal being detected by afourth latch circuit. The signal indicating changes in minutes will bereferred to as 60S↑. 60S↑. UDII* is a signal representing that oneminute has just passed after the signal UDII has been maintained at highlevel for a time interval of more than 4 seconds, with the timepiece inthe seconds zeroing mode. The command signal P₁ is the logical productof the signal 60S↑.UDII* and Q₅ D₆ T₂₄, and is utilized as a commandsignal to start the calculation for adjusting gain/loss. An outputsignal which is the logical product of signals 60S↑·UDII* and Q₉ isapplied to the reset input of the edge-triggered bistable. The output ofthe edge-triggered bistable flip-flop and signal 60S↑· UDII* are appliedto a gate whose output is applied to another gate to which signal Q₈ isalso applied, as shown in FIG. 47. This gate generates an output signalDGR, which is supplied to the reset input of the divide-by-two bistableof the date gate circuit 1482 so that the date gate circuit is reset toits starting state, i.e., the state of being ready to count to eightdays.

If the switch for zeroing the seconds display is depressed for less than4 seconds, the edge-triggered bistable of the input analyzing circuit1483 is not triggered and, therefore, a signal commanding gain/lossadjustment is not generated. As already noted hereinabove, the outputsignal P₁ is not generated until one minute has passed following theswitch being first depressed and, accordingly, it is possible to cancelthe application of the gain/loss adjusting signal by setting signalUDII* to the low level within one minute.

FIG. 49 shows a preferred example of the frequency adjusting pulsegenerting circuit. This circuit has already been discussed hereinaboveand, therefore, a detailed description is omitted here. 9n

What is claimed is:
 1. An electronic timepiece comprising:a frequencysupply for providing a relatively high frequency timebase signal; afrequency converter responsive to said timebase signal for providing arelatively low frequency time unit signal; timekeeping means responsiveto said time unit signal for providing current time information; meansfor correcting said current time information; display means fordisplaying said current time information; command means for generating acalculation command signal; circuit means enabled by said calculationcommand signal to produce, in response to said time unit signal afrequency error signal indicative of an error in the frequency of saidtime unit signal; means for generating a gain/loss adjustment signal inresponse to said frequency error signal; frequency adjusting circuitmeans for adjusting the frequency of said time unit signal in responseto said gain/loss adjustment signal; and external control meansresponsive to actuation for generating said calculation command signal;wherein said timekeeping means includes a seconds counter, and whereinsaid external control means is arranged to reset the seconds counter ofsaid timekeeping means and energize said command means simultaneouslywith the resetting of said seconds counter.
 2. An electronic timepiececomprising:a frequency supply for providing a relatively high frequencytimebase signal; a frequency converter responsive to said timebasesignal for providing a relatively low frequency time unit signal;timekeeping means responsive to said time unit signal for providingcurrent time information; means for correcting said current timeinformation; command means for generating a calculation command signal;circuit means enabled by said calculation command signal to produce, inresponse to said time unit signal, a frequency error signal indicativeof an error in the frequency of said time unit signal; means forgenerating a gain/loss adjustment signal in response to said frequencyerror signal; frequency adjusting circuit means for adjusting thefrequency of said time unit signal in response to said gain/lossadjustment signal; and external control means responsive to actuationfor generating said calculation command signal; in which said externalcontrol means is arranged to control both of said command means and saidcorrection means.
 3. An electronic timepiece comprising:a frequencysupply for providing a relatively high frequency timebase signal; afrequency converter responsive to said timebase signal for providing arelatively low frequency time unit signal; timekeeping means responsiveto said time unit signal for providing current time information; meansfor correcting said current time information; display means fordisplaying said current time information; command means for generating acalculation command signal; circuit means enabled by said calculationcommand signal to produce, in response to said time unit signal, afrequency error signal indicative of an error in the frequency of saidtime unit signal, said circuit means comprising first register means,second register means, a driving gate for driving both of said first andsecond register means and a comparator circuit for controlling saiddriving gate, said first register means including a counter circuit forcounting in response to said time unit signal, and said second registermeans including a counter circuit arranged to have a resetting functionand including an input connected to said driving gate;wherein said firstregister means, second register means, and comparator circuit constitutean electronic servo system, which forms a negative feedback loop circuitfor producing a compensation signal to compensate the error between thecurrent time kept by said first register means and new time data inputthrough said command means, with the compensation signal being kept insaid second register means to produce said error signal.
 4. Anelectronic timepiece according to claim 3, wherein the negative feedback loop circuit has the loop gain of more than or equal to minus onefor the error compensation.
 5. An electronic timepiece having a sourceof a relatively high frequency timebase signal, frequency convertermeans responsive to said timebase signal for providing a relatively lowfrequency time unit signal, timekeeping register means responsive tosaid time unit signal for producing current time information signalsindicative of current time, and a timekeeping rate gain/loss adjustmentsystem for automatic correction of the timekeeping rate of saidelectronic timepiece, comprising:externally actuatable means forgenerating a first control signal in response to a first actuationthereof and for generating a second control signal in response to asecond actuation thereof, said second actuation being initiatedfollowing a predetermined correction time interval after the initiationof said first actuation; first counter circuit means coupled to receivesaid unit time signal for counting successive periods thereof; saidfirst counter circuit means being responsive to said first controlsignal for being set to a predetermined initial count value; memorycircuit means, operable to produce output signals indicative of anumeric value stored therein; transfer circuit means coupled to saidfirst counter circuit means and to said memory circuit means, andresponsive to said second control signal for modifying a numeric valuestored in said memory circuit by an amount determined by the count valueheld in said counter circuit means at the time of generation of saidsecond control signal; feedback signal generation circuit meansresponsive to signals produced by said memory circuit means forproducing a feedback signal comprising a train of pulses whose frequencyis determined in accordance with the magnitude of said numeric valuestored in said memory circuit means; frequency combining means coupledbetween said timebase signal source and said frequency converter means,for combining said timebase signal with said feedback signal for therebyproducing an output signal to be applied to said frequency convertermeans; whereby the magnitude of said numeric value stored into saidmemory circuit means by said second control signal represents adeviation of the frequency of said unit time signal from said correcttimekeeping rate, and whereby said feedback signal frequency is suchthat said output signal from said frequency combining means results insaid time unit signal from said frequency converter means attaining adesired correct timekeeping rate; and initial reset means coupled tosaid memory circuit means, for setting the contents thereof to apredetermined initial value and for simultaneously setting the contentsof said first counter circuit means to said predetermined initial countvalue, said simultaneous setting of said memory circuit and firstcounter circuit means being performed at the commencement of timekeepingoperation by said electronic timepiece; said memory circuit meanscomprising second counter circuit means having an identical number ofstages and maximum count value to said first counter circuit means; saidfrequency converter means further producing a train of relatively highfrequency timing pulses, and further comprising first gate circuit meansfor detecting said maximum count value of said first counter circuitmeans and for producing an output signal indicative thereof, bistablecircuit means responsive to said second control signal for initiatinggeneration of a gating signal and responsive to said output signal fromsaid first gate circuit means for terminating generation of said gatingsignal, and second gate circuit means responsive to said gating signalfor transferring said relatively high frequency timing pulses to anoutput terminal thereof, said output terminal being coupled to inputterminals of said first and second counter circuit means, wherebyinitiation of said second control signal causes said timing pulses to beinput to said first and second counter circuit means until said maximumcount value of said first counter circuit means is attained, whereby acount value is stored in said second counter circuit means having avalue which is the difference between the contents of said secondcounter circuit means prior to initiation of said second control signaland the count value stored in said first counter circuit means prior toinitiation of said second control signal.
 6. An electronic timepiecehaving a source of a relatively high frequency timebase signal,frequency converter means responsive to said timebase signal forproviding a relatively low frequency time unit signal, timekeepingregister means responsive to said time unit signal for producing currenttime information signals indicative of current time, and a timekeepingrate gain/loss adjustment system for automatic correction of thetimekeeping rate of said electronic timepiece, comprising:externallyactuatable means for generating a first control signal in response to afirst actuation thereof and for generating a second control signal inresponse to a second actuation thereof, said second actuation beinginitiated following a predetermined correction time interval after theinitiation of said first actuation; first counter circuit means coupledto receive said unit time signal for counting successive periodsthereof; said first counter circuit means being responsive to said firstcontrol signal for being set to a predetermined initial count value;memory circuit means, operable to produce output signals indicative of anumeric value stored therein; transfer circuit means coupled to saidfirst counter circuit means and to said memory circuit means, andresponsive to said second control signal for modifying a numeric valuestored in said memory circuit by an amount determined by the count valueheld in said counter circuit means at the time of generation of saidsecond control signal; feedback signal generation circuit meansresponsive to signals produced by said memory circuit means forproducing a feedback signal comprising a train of pulses whose frequencyis determined in accordance with the magnitude of said numeric valuestored in said memory circuit means; and frequency combining meanscoupled between said timebase signal source and said frequency convertermeans, for combining said timebase signal with said feedback signal forthereby producing an output signal to be applied to said frequencyconverter means; whereby the magnitude of said numeric value stored intosaid memory circuit means by said second control signal represents adeviation of the frequency of said unit time signal from said correcttimekeeping rate, and whereby said feedback signal frequency is suchthat said output signal from said frequency combining means results insaid time unit signal from said frequency converter means attaining adesired correct timekeeping rate; wherein said frequency converter meansproduces a plurality of timing signals of different frequencies, andwherein said memory circuit means produces a plurality of output signalsindicative of the contents thereof, each of said output signals having apredetermined weight value allocated thereto, and further wherein saidfeedback signal generation circuit means includes a plurality offrequency selecting gate circuits each responsive to a predetermined oneof said frequency converter output signals for passing a correspondingpredetermined one of said timing signals to an output thereof, saidfeedback signal generation circuit means further including frequencycombining circuit means responsive to the totality of said outputs fromsaid frequency selecting gate circuits for producing said feedbacksignal as a signal whose frequency is proportional to the sum of thefrequencies of each of said timing signals passed by said frequencyselecting gate circuits.
 7. An electronic timepiece having a source of arelatively high frequency timebase signal, frequency converter meansresponsive to said timebase signal for providing a relatively lowfrequency time unit signal, timekeeping register means responsive tosaid time unit signal for producing current time information signalsindicative of current time, and a timekeeping rate gain/loss adjustmentsystem for automatic correction of the timekeeping rate of saidelectronic timepiece, comprising:externally actuatable means forgenerating a first control signal in response to a first actuationthereof and for generating a second control signal in response to asecond actuation thereof, said second actuation being initiatedfollowing a predetermined correction time interval after the initiationof said first actuation; first counter circuit means coupled to receivesaid unit time signal for counting successive periods thereof; saidfirst counter circuit means being responsive to said first controlsignal for being set to a predetermined initial count value; memorycircuit means, operable to produce output signals indicative of anumeric value stored therein; transfer circuit means coupled to saidfirst counter circuit means and to said memory circuit means, andresponsive to said second control signal for modifying a numeric valuestored in said memory circuit by an amount determined by the count valueheld in said counter circuit means at the time of generation of saidsecond control signal; feedback signal generation circuit meansresponsive to signals produced by said memory circuit means forproducing a feedback signal comprising a train of pulses whose frequencyis determined in accordance with the magnitude of said numeric valuestored in said memory circuit means; frequency combining means coupledbetween said timebase signal source and said frequency converter means,for combining said timebase signal with said feedback singal for therebyproducing an output signal to be applied to said frequency convertermeans; whereby the magnitude of said numeric value stored into saidmemory circuit means by said second control signal represents adeviation of the frequency of said unit time signal from said correcttimekeeping rate, and whereby said feedback signal frequency is suchthat said output signal from said frequency combining means results insaid time unit signal from said frequency converter means attaining adesired correct timekeeping rate; counter means for counting one of saidcurrent time information signals and responsive to said first controlsignal from said externally actuatable means for being reset to apredetermined initial count value, said counter means thereby producinga correction enabling signal after a predetermined time interval haselapsed following the initiation of said first control signal; and gatecircuit means responsive to said correction enabling signal fortransferring said second control signal to said transfer circuit means,and responsive to said second control signal in the absence of saidcorrection enabling signal for inhibiting transfer of said secondcontrol signal to said transfer circuit means and for setting said firstcounter circuit means to said initial count value thereof.
 8. Anelectronic timepiece according to claim 7, in which said current timeinformation counter means comprises a counter which is incremented by acurrent time information signal once per day and which produces saidcorrection enabling signal during a predetermined interval of one dayafter a predetermined number of days following initiation of said firstcontrol signal.